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CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492)
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@ -454,6 +454,7 @@ namespace ARMeilleure.Decoders
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SetA64("x00111100x100010000000xxxxxxxxxx", InstName.Scvtf_Gp, InstEmit.Scvtf_Gp, typeof(OpCodeSimdCvt));
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SetA64("x00111100x100010000000xxxxxxxxxx", InstName.Scvtf_Gp, InstEmit.Scvtf_Gp, typeof(OpCodeSimdCvt));
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SetA64(">00111100x000010>xxxxxxxxxxxxxxx", InstName.Scvtf_Gp_Fixed, InstEmit.Scvtf_Gp_Fixed, typeof(OpCodeSimdCvt));
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SetA64(">00111100x000010>xxxxxxxxxxxxxxx", InstName.Scvtf_Gp_Fixed, InstEmit.Scvtf_Gp_Fixed, typeof(OpCodeSimdCvt));
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SetA64("010111100x100001110110xxxxxxxxxx", InstName.Scvtf_S, InstEmit.Scvtf_S, typeof(OpCodeSimd));
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SetA64("010111100x100001110110xxxxxxxxxx", InstName.Scvtf_S, InstEmit.Scvtf_S, typeof(OpCodeSimd));
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SetA64("010111110>>xxxxx111001xxxxxxxxxx", InstName.Scvtf_S_Fixed, InstEmit.Scvtf_S_Fixed, typeof(OpCodeSimdShImm));
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SetA64("0>0011100<100001110110xxxxxxxxxx", InstName.Scvtf_V, InstEmit.Scvtf_V, typeof(OpCodeSimd));
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SetA64("0>0011100<100001110110xxxxxxxxxx", InstName.Scvtf_V, InstEmit.Scvtf_V, typeof(OpCodeSimd));
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SetA64("0x001111001xxxxx111001xxxxxxxxxx", InstName.Scvtf_V_Fixed, InstEmit.Scvtf_V_Fixed, typeof(OpCodeSimdShImm));
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SetA64("0x001111001xxxxx111001xxxxxxxxxx", InstName.Scvtf_V_Fixed, InstEmit.Scvtf_V_Fixed, typeof(OpCodeSimdShImm));
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SetA64("0100111101xxxxxx111001xxxxxxxxxx", InstName.Scvtf_V_Fixed, InstEmit.Scvtf_V_Fixed, typeof(OpCodeSimdShImm));
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SetA64("0100111101xxxxxx111001xxxxxxxxxx", InstName.Scvtf_V_Fixed, InstEmit.Scvtf_V_Fixed, typeof(OpCodeSimdShImm));
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@ -576,6 +577,7 @@ namespace ARMeilleure.Decoders
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SetA64("x00111100x100011000000xxxxxxxxxx", InstName.Ucvtf_Gp, InstEmit.Ucvtf_Gp, typeof(OpCodeSimdCvt));
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SetA64("x00111100x100011000000xxxxxxxxxx", InstName.Ucvtf_Gp, InstEmit.Ucvtf_Gp, typeof(OpCodeSimdCvt));
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SetA64(">00111100x000011>xxxxxxxxxxxxxxx", InstName.Ucvtf_Gp_Fixed, InstEmit.Ucvtf_Gp_Fixed, typeof(OpCodeSimdCvt));
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SetA64(">00111100x000011>xxxxxxxxxxxxxxx", InstName.Ucvtf_Gp_Fixed, InstEmit.Ucvtf_Gp_Fixed, typeof(OpCodeSimdCvt));
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SetA64("011111100x100001110110xxxxxxxxxx", InstName.Ucvtf_S, InstEmit.Ucvtf_S, typeof(OpCodeSimd));
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SetA64("011111100x100001110110xxxxxxxxxx", InstName.Ucvtf_S, InstEmit.Ucvtf_S, typeof(OpCodeSimd));
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SetA64("011111110>>xxxxx111001xxxxxxxxxx", InstName.Ucvtf_S_Fixed, InstEmit.Ucvtf_S_Fixed, typeof(OpCodeSimdShImm));
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SetA64("0>1011100<100001110110xxxxxxxxxx", InstName.Ucvtf_V, InstEmit.Ucvtf_V, typeof(OpCodeSimd));
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SetA64("0>1011100<100001110110xxxxxxxxxx", InstName.Ucvtf_V, InstEmit.Ucvtf_V, typeof(OpCodeSimd));
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SetA64("0x101111001xxxxx111001xxxxxxxxxx", InstName.Ucvtf_V_Fixed, InstEmit.Ucvtf_V_Fixed, typeof(OpCodeSimdShImm));
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SetA64("0x101111001xxxxx111001xxxxxxxxxx", InstName.Ucvtf_V_Fixed, InstEmit.Ucvtf_V_Fixed, typeof(OpCodeSimdShImm));
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SetA64("0110111101xxxxxx111001xxxxxxxxxx", InstName.Ucvtf_V_Fixed, InstEmit.Ucvtf_V_Fixed, typeof(OpCodeSimdShImm));
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SetA64("0110111101xxxxxx111001xxxxxxxxxx", InstName.Ucvtf_V_Fixed, InstEmit.Ucvtf_V_Fixed, typeof(OpCodeSimdShImm));
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@ -494,15 +494,19 @@ namespace ARMeilleure.Instructions
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}
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}
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else
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else
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{
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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EmitCvtf(context, signed: true, scalar: true);
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}
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}
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int sizeF = op.Size & 1;
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public static void Scvtf_S_Fixed(ArmEmitterContext context)
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{
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Operand res = EmitVectorLongExtract(context, op.Rn, 0, sizeF + 2);
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if (Optimizations.UseSse2)
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{
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res = EmitFPConvert(context, res, op.Size, signed: true);
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EmitSse2ScvtfOp(context, scalar: true);
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}
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context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
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else
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{
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EmitCvtf(context, signed: true, scalar: true);
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}
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}
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}
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}
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@ -514,7 +518,7 @@ namespace ARMeilleure.Instructions
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}
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}
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else
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else
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{
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{
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EmitVectorCvtf(context, signed: true);
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EmitCvtf(context, signed: true, scalar: false);
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}
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}
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}
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}
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@ -526,7 +530,7 @@ namespace ARMeilleure.Instructions
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}
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}
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else
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else
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{
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{
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EmitVectorCvtf(context, signed: true);
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EmitCvtf(context, signed: true, scalar: false);
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}
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}
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}
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}
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@ -562,15 +566,19 @@ namespace ARMeilleure.Instructions
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}
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}
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else
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else
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{
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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EmitCvtf(context, signed: false, scalar: true);
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}
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}
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int sizeF = op.Size & 1;
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public static void Ucvtf_S_Fixed(ArmEmitterContext context)
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{
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Operand ne = EmitVectorLongExtract(context, op.Rn, 0, sizeF + 2);
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if (Optimizations.UseSse2)
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{
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Operand res = EmitFPConvert(context, ne, sizeF, signed: false);
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EmitSse2UcvtfOp(context, scalar: true);
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}
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context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
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else
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{
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EmitCvtf(context, signed: false, scalar: true);
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}
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}
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}
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}
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@ -582,7 +590,7 @@ namespace ARMeilleure.Instructions
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}
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}
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else
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else
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{
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{
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EmitVectorCvtf(context, signed: false);
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EmitCvtf(context, signed: false, scalar: false);
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}
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}
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}
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}
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@ -594,7 +602,7 @@ namespace ARMeilleure.Instructions
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}
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}
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else
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else
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{
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{
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EmitVectorCvtf(context, signed: false);
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EmitCvtf(context, signed: false, scalar: false);
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}
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}
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}
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}
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@ -742,7 +750,7 @@ namespace ARMeilleure.Instructions
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SetIntOrZR(context, op.Rd, res);
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SetIntOrZR(context, op.Rd, res);
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}
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}
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private static void EmitVectorCvtf(ArmEmitterContext context, bool signed)
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private static void EmitCvtf(ArmEmitterContext context, bool signed, bool scalar)
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{
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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@ -753,7 +761,7 @@ namespace ARMeilleure.Instructions
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int fBits = GetFBits(context);
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int fBits = GetFBits(context);
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int elems = op.GetBytesCount() >> sizeI;
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int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
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for (int index = 0; index < elems; index++)
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for (int index = 0; index < elems; index++)
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{
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{
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@ -315,6 +315,7 @@ namespace ARMeilleure.Instructions
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Scvtf_Gp,
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Scvtf_Gp,
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Scvtf_Gp_Fixed,
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Scvtf_Gp_Fixed,
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Scvtf_S,
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Scvtf_S,
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Scvtf_S_Fixed,
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Scvtf_V,
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Scvtf_V,
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Scvtf_V_Fixed,
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Scvtf_V_Fixed,
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Sha1c_V,
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Sha1c_V,
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@ -414,6 +415,7 @@ namespace ARMeilleure.Instructions
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Ucvtf_Gp,
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Ucvtf_Gp,
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Ucvtf_Gp_Fixed,
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Ucvtf_Gp_Fixed,
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Ucvtf_S,
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Ucvtf_S,
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Ucvtf_S_Fixed,
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Ucvtf_V,
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Ucvtf_V,
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Ucvtf_V_Fixed,
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Ucvtf_V_Fixed,
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Uhadd_V,
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Uhadd_V,
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@ -195,6 +195,24 @@ namespace Ryujinx.Tests.Cpu
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};
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};
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}
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}
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private static uint[] _SU_Cvt_F_S_Fixed_S_()
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{
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return new uint[]
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{
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0x5F20E420u, // SCVTF S0, S1, #32
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0x7F20E420u // UCVTF S0, S1, #32
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};
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}
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private static uint[] _SU_Cvt_F_S_Fixed_D_()
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{
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return new uint[]
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{
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0x5F40E420u, // SCVTF D0, D1, #64
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0x7F40E420u // UCVTF D0, D1, #64
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};
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}
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private static uint[] _SU_Cvt_F_V_Fixed_2S_4S_()
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private static uint[] _SU_Cvt_F_V_Fixed_2S_4S_()
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{
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{
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return new uint[]
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return new uint[]
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@ -523,6 +541,42 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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CompareAgainstUnicorn();
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}
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}
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[Test, Pairwise] [Explicit]
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public void SU_Cvt_F_S_Fixed_S([ValueSource("_SU_Cvt_F_S_Fixed_S_")] uint opcodes,
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[ValueSource("_1S_")] [Random(RndCnt)] ulong a,
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[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
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{
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uint immHb = (64 - fBits) & 0x7F;
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opcodes |= (immHb << 16);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0(a);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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public void SU_Cvt_F_S_Fixed_D([ValueSource("_SU_Cvt_F_S_Fixed_D_")] uint opcodes,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
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[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
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{
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uint immHb = (128 - fBits) & 0x7F;
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opcodes |= (immHb << 16);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE1(z);
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V128 v1 = MakeVectorE0(a);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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[Test, Pairwise] [Explicit]
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public void SU_Cvt_F_V_Fixed_2S_4S([ValueSource("_SU_Cvt_F_V_Fixed_2S_4S_")] uint opcodes,
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public void SU_Cvt_F_V_Fixed_2S_4S([ValueSource("_SU_Cvt_F_V_Fixed_2S_4S_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(0u)] uint rd,
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