mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-09-10 21:53:18 +02:00
Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)
This commit is contained in:
parent
53b9267b47
commit
4bd1ad16f9
@ -485,12 +485,16 @@ namespace ARMeilleure.Decoders
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SetA64("01011110101xxxxx101101xxxxxxxxxx", InstName.Sqdmulh_S, InstEmit.Sqdmulh_S, OpCodeSimdReg.Create);
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SetA64("01011110101xxxxx101101xxxxxxxxxx", InstName.Sqdmulh_S, InstEmit.Sqdmulh_S, OpCodeSimdReg.Create);
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SetA64("0x001110011xxxxx101101xxxxxxxxxx", InstName.Sqdmulh_V, InstEmit.Sqdmulh_V, OpCodeSimdReg.Create);
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SetA64("0x001110011xxxxx101101xxxxxxxxxx", InstName.Sqdmulh_V, InstEmit.Sqdmulh_V, OpCodeSimdReg.Create);
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SetA64("0x001110101xxxxx101101xxxxxxxxxx", InstName.Sqdmulh_V, InstEmit.Sqdmulh_V, OpCodeSimdReg.Create);
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SetA64("0x001110101xxxxx101101xxxxxxxxxx", InstName.Sqdmulh_V, InstEmit.Sqdmulh_V, OpCodeSimdReg.Create);
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SetA64("0x00111101xxxxxx1100x0xxxxxxxxxx", InstName.Sqdmulh_Ve, InstEmit.Sqdmulh_Ve, OpCodeSimdRegElem.Create);
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SetA64("0x00111110xxxxxx1100x0xxxxxxxxxx", InstName.Sqdmulh_Ve, InstEmit.Sqdmulh_Ve, OpCodeSimdRegElem.Create);
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SetA64("01111110xx100000011110xxxxxxxxxx", InstName.Sqneg_S, InstEmit.Sqneg_S, OpCodeSimd.Create);
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SetA64("01111110xx100000011110xxxxxxxxxx", InstName.Sqneg_S, InstEmit.Sqneg_S, OpCodeSimd.Create);
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SetA64("0>101110<<100000011110xxxxxxxxxx", InstName.Sqneg_V, InstEmit.Sqneg_V, OpCodeSimd.Create);
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SetA64("0>101110<<100000011110xxxxxxxxxx", InstName.Sqneg_V, InstEmit.Sqneg_V, OpCodeSimd.Create);
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SetA64("01111110011xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_S, InstEmit.Sqrdmulh_S, OpCodeSimdReg.Create);
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SetA64("01111110011xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_S, InstEmit.Sqrdmulh_S, OpCodeSimdReg.Create);
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SetA64("01111110101xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_S, InstEmit.Sqrdmulh_S, OpCodeSimdReg.Create);
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SetA64("01111110101xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_S, InstEmit.Sqrdmulh_S, OpCodeSimdReg.Create);
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SetA64("0x101110011xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_V, InstEmit.Sqrdmulh_V, OpCodeSimdReg.Create);
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SetA64("0x101110011xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_V, InstEmit.Sqrdmulh_V, OpCodeSimdReg.Create);
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SetA64("0x101110101xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_V, InstEmit.Sqrdmulh_V, OpCodeSimdReg.Create);
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SetA64("0x101110101xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_V, InstEmit.Sqrdmulh_V, OpCodeSimdReg.Create);
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SetA64("0x00111101xxxxxx1101x0xxxxxxxxxx", InstName.Sqrdmulh_Ve, InstEmit.Sqrdmulh_Ve, OpCodeSimdRegElem.Create);
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SetA64("0x00111110xxxxxx1101x0xxxxxxxxxx", InstName.Sqrdmulh_Ve, InstEmit.Sqrdmulh_Ve, OpCodeSimdRegElem.Create);
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SetA64("0>001110<<1xxxxx010111xxxxxxxxxx", InstName.Sqrshl_V, InstEmit.Sqrshl_V, OpCodeSimdReg.Create);
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SetA64("0>001110<<1xxxxx010111xxxxxxxxxx", InstName.Sqrshl_V, InstEmit.Sqrshl_V, OpCodeSimdReg.Create);
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SetA64("0101111100>>>xxx100111xxxxxxxxxx", InstName.Sqrshrn_S, InstEmit.Sqrshrn_S, OpCodeSimdShImm.Create);
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SetA64("0101111100>>>xxx100111xxxxxxxxxx", InstName.Sqrshrn_S, InstEmit.Sqrshrn_S, OpCodeSimdShImm.Create);
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SetA64("0x00111100>>>xxx100111xxxxxxxxxx", InstName.Sqrshrn_V, InstEmit.Sqrshrn_V, OpCodeSimdShImm.Create);
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SetA64("0x00111100>>>xxx100111xxxxxxxxxx", InstName.Sqrshrn_V, InstEmit.Sqrshrn_V, OpCodeSimdShImm.Create);
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@ -2642,22 +2642,27 @@ namespace ARMeilleure.Instructions
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public static void Sqadd_S(ArmEmitterContext context)
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public static void Sqadd_S(ArmEmitterContext context)
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{
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{
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EmitScalarSaturatingBinaryOpSx(context, SaturatingFlags.Add);
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EmitScalarSaturatingBinaryOpSx(context, flags: SaturatingFlags.Add);
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}
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}
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public static void Sqadd_V(ArmEmitterContext context)
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public static void Sqadd_V(ArmEmitterContext context)
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{
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{
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EmitVectorSaturatingBinaryOpSx(context, SaturatingFlags.Add);
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EmitVectorSaturatingBinaryOpSx(context, flags: SaturatingFlags.Add);
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}
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}
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public static void Sqdmulh_S(ArmEmitterContext context)
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public static void Sqdmulh_S(ArmEmitterContext context)
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{
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{
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EmitSaturatingBinaryOp(context, (op1, op2) => EmitDoublingMultiplyHighHalf(context, op1, op2, round: false), SaturatingFlags.ScalarSx);
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EmitScalarSaturatingBinaryOpSx(context, (op1, op2) => EmitDoublingMultiplyHighHalf(context, op1, op2, round: false));
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}
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}
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public static void Sqdmulh_V(ArmEmitterContext context)
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public static void Sqdmulh_V(ArmEmitterContext context)
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{
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{
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EmitSaturatingBinaryOp(context, (op1, op2) => EmitDoublingMultiplyHighHalf(context, op1, op2, round: false), SaturatingFlags.VectorSx);
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EmitVectorSaturatingBinaryOpSx(context, (op1, op2) => EmitDoublingMultiplyHighHalf(context, op1, op2, round: false));
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}
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public static void Sqdmulh_Ve(ArmEmitterContext context)
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{
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EmitVectorSaturatingBinaryOpByElemSx(context, (op1, op2) => EmitDoublingMultiplyHighHalf(context, op1, op2, round: false));
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}
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}
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public static void Sqneg_S(ArmEmitterContext context)
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public static void Sqneg_S(ArmEmitterContext context)
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@ -2672,22 +2677,27 @@ namespace ARMeilleure.Instructions
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public static void Sqrdmulh_S(ArmEmitterContext context)
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public static void Sqrdmulh_S(ArmEmitterContext context)
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{
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{
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EmitSaturatingBinaryOp(context, (op1, op2) => EmitDoublingMultiplyHighHalf(context, op1, op2, round: true), SaturatingFlags.ScalarSx);
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EmitScalarSaturatingBinaryOpSx(context, (op1, op2) => EmitDoublingMultiplyHighHalf(context, op1, op2, round: true));
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}
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}
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public static void Sqrdmulh_V(ArmEmitterContext context)
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public static void Sqrdmulh_V(ArmEmitterContext context)
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{
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{
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EmitSaturatingBinaryOp(context, (op1, op2) => EmitDoublingMultiplyHighHalf(context, op1, op2, round: true), SaturatingFlags.VectorSx);
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EmitVectorSaturatingBinaryOpSx(context, (op1, op2) => EmitDoublingMultiplyHighHalf(context, op1, op2, round: true));
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}
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public static void Sqrdmulh_Ve(ArmEmitterContext context)
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{
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EmitVectorSaturatingBinaryOpByElemSx(context, (op1, op2) => EmitDoublingMultiplyHighHalf(context, op1, op2, round: true));
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}
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}
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public static void Sqsub_S(ArmEmitterContext context)
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public static void Sqsub_S(ArmEmitterContext context)
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{
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{
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EmitScalarSaturatingBinaryOpSx(context, SaturatingFlags.Sub);
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EmitScalarSaturatingBinaryOpSx(context, flags: SaturatingFlags.Sub);
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}
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}
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public static void Sqsub_V(ArmEmitterContext context)
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public static void Sqsub_V(ArmEmitterContext context)
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{
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{
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EmitVectorSaturatingBinaryOpSx(context, SaturatingFlags.Sub);
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EmitVectorSaturatingBinaryOpSx(context, flags: SaturatingFlags.Sub);
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}
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}
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public static void Sqxtn_S(ArmEmitterContext context)
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public static void Sqxtn_S(ArmEmitterContext context)
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@ -2850,12 +2860,12 @@ namespace ARMeilleure.Instructions
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public static void Suqadd_S(ArmEmitterContext context)
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public static void Suqadd_S(ArmEmitterContext context)
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{
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{
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EmitScalarSaturatingBinaryOpSx(context, SaturatingFlags.Accumulate);
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EmitScalarSaturatingBinaryOpSx(context, flags: SaturatingFlags.Accumulate);
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}
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}
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public static void Suqadd_V(ArmEmitterContext context)
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public static void Suqadd_V(ArmEmitterContext context)
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{
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{
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EmitVectorSaturatingBinaryOpSx(context, SaturatingFlags.Accumulate);
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EmitVectorSaturatingBinaryOpSx(context, flags: SaturatingFlags.Accumulate);
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}
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}
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public static void Uaba_V(ArmEmitterContext context)
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public static void Uaba_V(ArmEmitterContext context)
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@ -1302,32 +1302,29 @@ namespace ARMeilleure.Instructions
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[Flags]
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[Flags]
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public enum SaturatingFlags
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public enum SaturatingFlags
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{
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{
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Scalar = 1 << 0,
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None = 0,
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Signed = 1 << 1,
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Add = 1 << 2,
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ByElem = 1 << 0,
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Sub = 1 << 3,
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Scalar = 1 << 1,
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Signed = 1 << 2,
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Accumulate = 1 << 4,
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Add = 1 << 3,
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Sub = 1 << 4,
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ScalarSx = Scalar | Signed,
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Accumulate = 1 << 5
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ScalarZx = Scalar,
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VectorSx = Signed,
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VectorZx = 0
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}
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}
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public static void EmitScalarSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit)
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public static void EmitScalarSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit)
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{
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{
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EmitSaturatingUnaryOpSx(context, emit, SaturatingFlags.ScalarSx);
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EmitSaturatingUnaryOpSx(context, emit, SaturatingFlags.Scalar | SaturatingFlags.Signed);
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}
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}
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public static void EmitVectorSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit)
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public static void EmitVectorSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit)
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{
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{
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EmitSaturatingUnaryOpSx(context, emit, SaturatingFlags.VectorSx);
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EmitSaturatingUnaryOpSx(context, emit, SaturatingFlags.Signed);
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}
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}
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private static void EmitSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit, SaturatingFlags flags)
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public static void EmitSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit, SaturatingFlags flags)
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{
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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@ -1357,24 +1354,29 @@ namespace ARMeilleure.Instructions
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context.Copy(GetVec(op.Rd), res);
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context.Copy(GetVec(op.Rd), res);
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}
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}
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public static void EmitScalarSaturatingBinaryOpSx(ArmEmitterContext context, SaturatingFlags flags)
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public static void EmitScalarSaturatingBinaryOpSx(ArmEmitterContext context, Func2I emit = null, SaturatingFlags flags = SaturatingFlags.None)
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{
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{
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EmitSaturatingBinaryOp(context, null, SaturatingFlags.ScalarSx | flags);
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EmitSaturatingBinaryOp(context, emit, SaturatingFlags.Scalar | SaturatingFlags.Signed | flags);
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}
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}
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public static void EmitScalarSaturatingBinaryOpZx(ArmEmitterContext context, SaturatingFlags flags)
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public static void EmitScalarSaturatingBinaryOpZx(ArmEmitterContext context, SaturatingFlags flags)
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{
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{
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EmitSaturatingBinaryOp(context, null, SaturatingFlags.ScalarZx | flags);
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EmitSaturatingBinaryOp(context, null, SaturatingFlags.Scalar | flags);
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}
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}
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public static void EmitVectorSaturatingBinaryOpSx(ArmEmitterContext context, SaturatingFlags flags)
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public static void EmitVectorSaturatingBinaryOpSx(ArmEmitterContext context, Func2I emit = null, SaturatingFlags flags = SaturatingFlags.None)
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{
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{
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EmitSaturatingBinaryOp(context, null, SaturatingFlags.VectorSx | flags);
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EmitSaturatingBinaryOp(context, emit, SaturatingFlags.Signed | flags);
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}
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}
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public static void EmitVectorSaturatingBinaryOpZx(ArmEmitterContext context, SaturatingFlags flags)
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public static void EmitVectorSaturatingBinaryOpZx(ArmEmitterContext context, SaturatingFlags flags)
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{
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{
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EmitSaturatingBinaryOp(context, null, SaturatingFlags.VectorZx | flags);
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EmitSaturatingBinaryOp(context, null, flags);
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}
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public static void EmitVectorSaturatingBinaryOpByElemSx(ArmEmitterContext context, Func2I emit)
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{
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EmitSaturatingBinaryOp(context, emit, SaturatingFlags.ByElem | SaturatingFlags.Signed);
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}
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}
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public static void EmitSaturatingBinaryOp(ArmEmitterContext context, Func2I emit, SaturatingFlags flags)
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public static void EmitSaturatingBinaryOp(ArmEmitterContext context, Func2I emit, SaturatingFlags flags)
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@ -1383,6 +1385,7 @@ namespace ARMeilleure.Instructions
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Operand res = context.VectorZero();
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Operand res = context.VectorZero();
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bool byElem = (flags & SaturatingFlags.ByElem) != 0;
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bool scalar = (flags & SaturatingFlags.Scalar) != 0;
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bool scalar = (flags & SaturatingFlags.Scalar) != 0;
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bool signed = (flags & SaturatingFlags.Signed) != 0;
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bool signed = (flags & SaturatingFlags.Signed) != 0;
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@ -1395,13 +1398,11 @@ namespace ARMeilleure.Instructions
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if (add || sub)
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if (add || sub)
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{
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{
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OpCodeSimdReg opReg = (OpCodeSimdReg)op;
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for (int index = 0; index < elems; index++)
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for (int index = 0; index < elems; index++)
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{
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{
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Operand de;
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Operand de;
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Operand ne = EmitVectorExtract(context, opReg.Rn, index, op.Size, signed);
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Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size, signed);
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Operand me = EmitVectorExtract(context, opReg.Rm, index, op.Size, signed);
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Operand me = EmitVectorExtract(context, ((OpCodeSimdReg)op).Rm, index, op.Size, signed);
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if (op.Size <= 2)
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if (op.Size <= 2)
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{
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{
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@ -1445,12 +1446,23 @@ namespace ARMeilleure.Instructions
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}
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}
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else
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else
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{
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{
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OpCodeSimdReg opReg = (OpCodeSimdReg)op;
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Operand me = null;
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if (byElem)
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{
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OpCodeSimdRegElem opRegElem = (OpCodeSimdRegElem)op;
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me = EmitVectorExtract(context, opRegElem.Rm, opRegElem.Index, op.Size, signed);
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}
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for (int index = 0; index < elems; index++)
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for (int index = 0; index < elems; index++)
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{
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{
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Operand ne = EmitVectorExtract(context, opReg.Rn, index, op.Size, signed);
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Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size, signed);
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Operand me = EmitVectorExtract(context, opReg.Rm, index, op.Size, signed);
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if (!byElem)
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{
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me = EmitVectorExtract(context, ((OpCodeSimdReg)op).Rm, index, op.Size, signed);
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}
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Operand de = EmitSatQ(context, emit(ne, me), op.Size, true, signed);
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Operand de = EmitSatQ(context, emit(ne, me), op.Size, true, signed);
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@ -358,10 +358,12 @@ namespace ARMeilleure.Instructions
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Sqadd_V,
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Sqadd_V,
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Sqdmulh_S,
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Sqdmulh_S,
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Sqdmulh_V,
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Sqdmulh_V,
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Sqdmulh_Ve,
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Sqneg_S,
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Sqneg_S,
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Sqneg_V,
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Sqneg_V,
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Sqrdmulh_S,
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Sqrdmulh_S,
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Sqrdmulh_V,
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Sqrdmulh_V,
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Sqrdmulh_Ve,
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Sqrshl_V,
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Sqrshl_V,
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Sqrshrn_S,
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Sqrshrn_S,
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Sqrshrn_V,
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Sqrshrn_V,
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@ -26,23 +26,27 @@ namespace Ryujinx.Tests.Cpu
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#endregion
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#endregion
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#region "ValueSource (Opcodes)"
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#region "ValueSource (Opcodes)"
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private static uint[] _Mla_Mls_Mul_Ve_4H_8H_()
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private static uint[] _Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_4H_8H_()
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{
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{
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return new uint[]
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return new uint[]
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{
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{
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0x2F400000u, // MLA V0.4H, V0.4H, V0.H[0]
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0x2F400000u, // MLA V0.4H, V0.4H, V0.H[0]
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0x2F404000u, // MLS V0.4H, V0.4H, V0.H[0]
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0x2F404000u, // MLS V0.4H, V0.4H, V0.H[0]
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0x0F408000u // MUL V0.4H, V0.4H, V0.H[0]
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0x0F408000u, // MUL V0.4H, V0.4H, V0.H[0]
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0x0F40C000u, // SQDMULH V0.4H, V0.4H, V0.H[0]
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0x0F40D000u // SQRDMULH V0.4H, V0.4H, V0.H[0]
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};
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};
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}
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}
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private static uint[] _Mla_Mls_Mul_Ve_2S_4S_()
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private static uint[] _Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_2S_4S_()
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{
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{
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return new uint[]
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return new uint[]
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{
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{
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0x2F800000u, // MLA V0.2S, V0.2S, V0.S[0]
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0x2F800000u, // MLA V0.2S, V0.2S, V0.S[0]
|
||||||
0x2F804000u, // MLS V0.2S, V0.2S, V0.S[0]
|
0x2F804000u, // MLS V0.2S, V0.2S, V0.S[0]
|
||||||
0x0F808000u // MUL V0.2S, V0.2S, V0.S[0]
|
0x0F808000u, // MUL V0.2S, V0.2S, V0.S[0]
|
||||||
|
0x0F80C000u, // SQDMULH V0.2S, V0.2S, V0.S[0]
|
||||||
|
0x0F80D000u // SQRDMULH V0.2S, V0.2S, V0.S[0]
|
||||||
};
|
};
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -77,15 +81,15 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
private const int RndCntIndex = 2;
|
private const int RndCntIndex = 2;
|
||||||
|
|
||||||
[Test, Pairwise]
|
[Test, Pairwise]
|
||||||
public void Mla_Mls_Mul_Ve_4H_8H([ValueSource("_Mla_Mls_Mul_Ve_4H_8H_")] uint opcodes,
|
public void Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_4H_8H([ValueSource(nameof(_Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_4H_8H_))] uint opcodes,
|
||||||
[Values(0u)] uint rd,
|
[Values(0u)] uint rd,
|
||||||
[Values(1u, 0u)] uint rn,
|
[Values(1u, 0u)] uint rn,
|
||||||
[Values(2u, 0u)] uint rm,
|
[Values(2u, 0u)] uint rm,
|
||||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
[ValueSource(nameof(_4H_))] [Random(RndCnt)] ulong z,
|
||||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
[ValueSource(nameof(_4H_))] [Random(RndCnt)] ulong a,
|
||||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong b,
|
[ValueSource(nameof(_4H_))] [Random(RndCnt)] ulong b,
|
||||||
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index,
|
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index,
|
||||||
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
|
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
|
||||||
{
|
{
|
||||||
uint h = (index >> 2) & 1;
|
uint h = (index >> 2) & 1;
|
||||||
uint l = (index >> 1) & 1;
|
uint l = (index >> 1) & 1;
|
||||||
@ -101,19 +105,19 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
|
|
||||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
|
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
|
||||||
|
|
||||||
CompareAgainstUnicorn();
|
CompareAgainstUnicorn(fpsrMask: Fpsr.Qc);
|
||||||
}
|
}
|
||||||
|
|
||||||
[Test, Pairwise]
|
[Test, Pairwise]
|
||||||
public void Mla_Mls_Mul_Ve_2S_4S([ValueSource("_Mla_Mls_Mul_Ve_2S_4S_")] uint opcodes,
|
public void Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_2S_4S([ValueSource(nameof(_Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_2S_4S_))] uint opcodes,
|
||||||
[Values(0u)] uint rd,
|
[Values(0u)] uint rd,
|
||||||
[Values(1u, 0u)] uint rn,
|
[Values(1u, 0u)] uint rn,
|
||||||
[Values(2u, 0u)] uint rm,
|
[Values(2u, 0u)] uint rm,
|
||||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
[ValueSource(nameof(_2S_))] [Random(RndCnt)] ulong z,
|
||||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
[ValueSource(nameof(_2S_))] [Random(RndCnt)] ulong a,
|
||||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong b,
|
[ValueSource(nameof(_2S_))] [Random(RndCnt)] ulong b,
|
||||||
[Values(0u, 1u, 2u, 3u)] uint index,
|
[Values(0u, 1u, 2u, 3u)] uint index,
|
||||||
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
||||||
{
|
{
|
||||||
uint h = (index >> 1) & 1;
|
uint h = (index >> 1) & 1;
|
||||||
uint l = index & 1;
|
uint l = index & 1;
|
||||||
@ -128,7 +132,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
|
|
||||||
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
|
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
|
||||||
|
|
||||||
CompareAgainstUnicorn();
|
CompareAgainstUnicorn(fpsrMask: Fpsr.Qc);
|
||||||
}
|
}
|
||||||
|
|
||||||
[Test, Pairwise]
|
[Test, Pairwise]
|
||||||
|
Loading…
Reference in New Issue
Block a user