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Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (fast paths). (#1630)
* Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (fast paths). * Ptc.InternalVersion = 1630 * Nits. * Address comments. * Update Ptc.cs * Address comment.
This commit is contained in:
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668720b088
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567ea726e1
@ -131,6 +131,7 @@ namespace ARMeilleure.CodeGen.X86
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Add(X86Instruction.Imul128, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x050000f7, InstructionFlags.None));
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Add(X86Instruction.Insertps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f3a21, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Jmp, new InstructionInfo(0x040000ff, BadOp, BadOp, BadOp, BadOp, InstructionFlags.None));
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Add(X86Instruction.Ldmxcsr, new InstructionInfo(0x02000fae, BadOp, BadOp, BadOp, BadOp, InstructionFlags.Vex));
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Add(X86Instruction.Lea, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x0000008d, InstructionFlags.None));
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Add(X86Instruction.Maxpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5f, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Maxps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5f, InstructionFlags.Vex));
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@ -257,6 +258,7 @@ namespace ARMeilleure.CodeGen.X86
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Add(X86Instruction.Sqrtps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f51, InstructionFlags.Vex));
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Add(X86Instruction.Sqrtsd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f51, InstructionFlags.Vex | InstructionFlags.PrefixF2));
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Add(X86Instruction.Sqrtss, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f51, InstructionFlags.Vex | InstructionFlags.PrefixF3));
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Add(X86Instruction.Stmxcsr, new InstructionInfo(0x03000fae, BadOp, BadOp, BadOp, BadOp, InstructionFlags.Vex));
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Add(X86Instruction.Sub, new InstructionInfo(0x00000029, 0x05000083, 0x05000081, BadOp, 0x0000002b, InstructionFlags.None));
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Add(X86Instruction.Subpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5c, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Subps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5c, InstructionFlags.Vex));
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@ -526,6 +528,11 @@ namespace ARMeilleure.CodeGen.X86
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WriteInstruction(dest, null, OperandType.None, X86Instruction.Jmp);
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}
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public void Ldmxcsr(Operand dest)
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{
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WriteInstruction(dest, null, OperandType.I32, X86Instruction.Ldmxcsr);
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}
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public void Lea(Operand dest, Operand source, OperandType type)
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{
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WriteInstruction(dest, source, type, X86Instruction.Lea);
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@ -796,6 +803,11 @@ namespace ARMeilleure.CodeGen.X86
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WriteOpCode(dest, null, null, OperandType.None, info.Flags, info.OpRRM | (int)condition);
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}
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public void Stmxcsr(Operand dest)
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{
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WriteInstruction(dest, null, OperandType.I32, X86Instruction.Stmxcsr);
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}
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public void Sub(Operand dest, Operand source, OperandType type)
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{
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WriteInstruction(dest, source, type, X86Instruction.Sub);
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@ -250,6 +250,40 @@ namespace ARMeilleure.CodeGen.X86
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break;
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}
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case IntrinsicType.Mxcsr:
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{
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Operand offset = operation.GetSource(0);
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Operand bits = operation.GetSource(1);
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Debug.Assert(offset.Kind == OperandKind.Constant && bits.Kind == OperandKind.Constant);
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Debug.Assert(offset.Type == OperandType.I32 && bits.Type == OperandType.I32);
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int offs = offset.AsInt32() + context.CallArgsRegionSize;
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Operand rsp = Register(X86Register.Rsp);
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MemoryOperand memOp = MemoryOp(OperandType.I32, rsp, null, Multiplier.x1, offs);
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Debug.Assert(HardwareCapabilities.SupportsSse || HardwareCapabilities.SupportsVexEncoding);
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context.Assembler.Stmxcsr(memOp);
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if (intrinOp.Intrinsic == Intrinsic.X86Mxcsrmb)
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{
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context.Assembler.Or(memOp, bits, OperandType.I32);
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}
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else /* if (intrinOp.Intrinsic == Intrinsic.X86Mxcsrub) */
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{
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Operand notBits = Const(~bits.AsInt32());
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context.Assembler.And(memOp, notBits, OperandType.I32);
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}
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context.Assembler.Ldmxcsr(memOp);
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break;
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}
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case IntrinsicType.PopCount:
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{
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Operand dest = operation.Destination;
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@ -76,6 +76,8 @@ namespace ARMeilleure.CodeGen.X86
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Add(Intrinsic.X86Mulps, new IntrinsicInfo(X86Instruction.Mulps, IntrinsicType.Binary));
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Add(Intrinsic.X86Mulsd, new IntrinsicInfo(X86Instruction.Mulsd, IntrinsicType.Binary));
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Add(Intrinsic.X86Mulss, new IntrinsicInfo(X86Instruction.Mulss, IntrinsicType.Binary));
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Add(Intrinsic.X86Mxcsrmb, new IntrinsicInfo(X86Instruction.None, IntrinsicType.Mxcsr)); // Mask bits.
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Add(Intrinsic.X86Mxcsrub, new IntrinsicInfo(X86Instruction.None, IntrinsicType.Mxcsr)); // Unmask bits.
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Add(Intrinsic.X86Paddb, new IntrinsicInfo(X86Instruction.Paddb, IntrinsicType.Binary));
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Add(Intrinsic.X86Paddd, new IntrinsicInfo(X86Instruction.Paddd, IntrinsicType.Binary));
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Add(Intrinsic.X86Paddq, new IntrinsicInfo(X86Instruction.Paddq, IntrinsicType.Binary));
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@ -3,6 +3,7 @@ namespace ARMeilleure.CodeGen.X86
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enum IntrinsicType
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{
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Comis_,
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Mxcsr,
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PopCount,
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Unary,
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UnaryToGpr,
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@ -114,6 +114,16 @@ namespace ARMeilleure.CodeGen.X86
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node = HandleVectorInsert8(block.Operations, node, operation);
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}
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break;
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case Instruction.Extended:
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IntrinsicOperation intrinOp = (IntrinsicOperation)operation;
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if (intrinOp.Intrinsic == Intrinsic.X86Mxcsrmb || intrinOp.Intrinsic == Intrinsic.X86Mxcsrub)
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{
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int stackOffset = stackAlloc.Allocate(OperandType.I32);
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operation.SetSources(new Operand[] { Const(stackOffset), operation.GetSource(0) });
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}
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break;
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}
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}
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}
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@ -2,6 +2,7 @@ namespace ARMeilleure.CodeGen.X86
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{
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enum X86Instruction
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{
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None,
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Add,
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Addpd,
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Addps,
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@ -60,6 +61,7 @@ namespace ARMeilleure.CodeGen.X86
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Imul128,
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Insertps,
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Jmp,
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Ldmxcsr,
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Lea,
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Maxpd,
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Maxps,
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@ -186,6 +188,7 @@ namespace ARMeilleure.CodeGen.X86
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Sqrtps,
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Sqrtsd,
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Sqrtss,
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Stmxcsr,
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Sub,
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Subpd,
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Subps,
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@ -380,15 +380,21 @@ namespace ARMeilleure.Instructions
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public static void Faddp_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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if (Optimizations.FastFP && Optimizations.UseSse41)
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{
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EmitSse2VectorPairwiseOpF(context, (op1, op2) =>
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{
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return EmitSse41ProcessNaNsOpF(context, (op1, op2) =>
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{
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return EmitSseOrAvxHandleFzModeOpF(context, (op1, op2) =>
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{
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IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
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Intrinsic addInst = (op.Size & 1) == 0 ? Intrinsic.X86Addps : Intrinsic.X86Addpd;
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return context.AddIntrinsic(addInst, op1, op2);
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}, scalar: false, op1, op2);
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}, scalar: false, op1, op2);
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});
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}
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else
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@ -478,8 +484,11 @@ namespace ARMeilleure.Instructions
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if (Optimizations.FastFP && Optimizations.UseSse41)
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{
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EmitSse41ProcessNaNsOpF(context, (op1, op2) =>
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{
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return EmitSseOrAvxHandleFzModeOpF(context, (op1, op2) =>
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{
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return EmitSse2VectorMaxMinOpF(context, op1, op2, isMax: true);
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}, scalar: true, op1, op2);
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}, scalar: true);
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}
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else
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@ -496,8 +505,11 @@ namespace ARMeilleure.Instructions
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if (Optimizations.FastFP && Optimizations.UseSse41)
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{
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EmitSse41ProcessNaNsOpF(context, (op1, op2) =>
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{
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return EmitSseOrAvxHandleFzModeOpF(context, (op1, op2) =>
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{
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return EmitSse2VectorMaxMinOpF(context, op1, op2, isMax: true);
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}, scalar: false, op1, op2);
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}, scalar: false);
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}
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else
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@ -582,9 +594,12 @@ namespace ARMeilleure.Instructions
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EmitSse2VectorPairwiseOpF(context, (op1, op2) =>
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{
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return EmitSse41ProcessNaNsOpF(context, (op1, op2) =>
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{
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return EmitSseOrAvxHandleFzModeOpF(context, (op1, op2) =>
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{
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return EmitSse2VectorMaxMinOpF(context, op1, op2, isMax: true);
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}, scalar: false, op1, op2);
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}, scalar: false, op1, op2);
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});
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}
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else
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@ -603,9 +618,12 @@ namespace ARMeilleure.Instructions
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EmitSse2VectorAcrossVectorOpF(context, (op1, op2) =>
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{
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return EmitSse41ProcessNaNsOpF(context, (op1, op2) =>
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{
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return EmitSseOrAvxHandleFzModeOpF(context, (op1, op2) =>
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{
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return EmitSse2VectorMaxMinOpF(context, op1, op2, isMax: true);
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}, scalar: false, op1, op2);
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}, scalar: false, op1, op2);
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});
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}
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else
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@ -622,8 +640,11 @@ namespace ARMeilleure.Instructions
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if (Optimizations.FastFP && Optimizations.UseSse41)
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{
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EmitSse41ProcessNaNsOpF(context, (op1, op2) =>
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{
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return EmitSseOrAvxHandleFzModeOpF(context, (op1, op2) =>
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{
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return EmitSse2VectorMaxMinOpF(context, op1, op2, isMax: false);
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}, scalar: true, op1, op2);
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}, scalar: true);
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}
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else
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@ -640,8 +661,11 @@ namespace ARMeilleure.Instructions
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if (Optimizations.FastFP && Optimizations.UseSse41)
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{
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EmitSse41ProcessNaNsOpF(context, (op1, op2) =>
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{
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return EmitSseOrAvxHandleFzModeOpF(context, (op1, op2) =>
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{
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return EmitSse2VectorMaxMinOpF(context, op1, op2, isMax: false);
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}, scalar: false, op1, op2);
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}, scalar: false);
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}
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else
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@ -726,9 +750,12 @@ namespace ARMeilleure.Instructions
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EmitSse2VectorPairwiseOpF(context, (op1, op2) =>
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{
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return EmitSse41ProcessNaNsOpF(context, (op1, op2) =>
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{
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return EmitSseOrAvxHandleFzModeOpF(context, (op1, op2) =>
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{
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return EmitSse2VectorMaxMinOpF(context, op1, op2, isMax: false);
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}, scalar: false, op1, op2);
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}, scalar: false, op1, op2);
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});
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}
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else
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@ -747,9 +774,12 @@ namespace ARMeilleure.Instructions
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EmitSse2VectorAcrossVectorOpF(context, (op1, op2) =>
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{
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return EmitSse41ProcessNaNsOpF(context, (op1, op2) =>
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{
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return EmitSseOrAvxHandleFzModeOpF(context, (op1, op2) =>
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{
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return EmitSse2VectorMaxMinOpF(context, op1, op2, isMax: false);
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}, scalar: false, op1, op2);
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}, scalar: false, op1, op2);
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});
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}
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else
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@ -3360,6 +3390,53 @@ namespace ARMeilleure.Instructions
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}
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}
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public static Operand EmitSseOrAvxHandleFzModeOpF(
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ArmEmitterContext context,
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Func2I emit,
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bool scalar,
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Operand n = null,
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Operand m = null)
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{
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Operand nCopy = n ?? context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rn));
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Operand mCopy = m ?? context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rm));
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EmitSseOrAvxEnterFtzAndDazModesOpF(context, out Operand isTrue);
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Operand res = emit(nCopy, mCopy);
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EmitSseOrAvxExitFtzAndDazModesOpF(context, isTrue);
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if (n != null || m != null)
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{
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return res;
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}
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int sizeF = ((IOpCodeSimd)context.CurrOp).Size & 1;
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if (sizeF == 0)
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{
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if (scalar)
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{
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res = context.VectorZeroUpper96(res);
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}
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else if (((OpCodeSimdReg)context.CurrOp).RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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}
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else /* if (sizeF == 1) */
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{
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if (scalar)
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{
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res = context.VectorZeroUpper64(res);
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}
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}
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context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rd), res);
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return null;
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}
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private static Operand EmitSse2VectorMaxMinOpF(ArmEmitterContext context, Operand n, Operand m, bool isMax)
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{
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IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
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@ -3418,8 +3495,11 @@ namespace ARMeilleure.Instructions
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mCopy = context.AddIntrinsic(Intrinsic.X86Blendvps, mCopy, negInfMask, mMask);
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Operand res = EmitSse41ProcessNaNsOpF(context, (op1, op2) =>
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{
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return EmitSseOrAvxHandleFzModeOpF(context, (op1, op2) =>
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{
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return EmitSse2VectorMaxMinOpF(context, op1, op2, isMax: isMaxNum);
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}, scalar: scalar, op1, op2);
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}, scalar: scalar, nCopy, mCopy);
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if (n != null || m != null)
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@ -3453,8 +3533,11 @@ namespace ARMeilleure.Instructions
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mCopy = context.AddIntrinsic(Intrinsic.X86Blendvpd, mCopy, negInfMask, mMask);
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Operand res = EmitSse41ProcessNaNsOpF(context, (op1, op2) =>
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{
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return EmitSseOrAvxHandleFzModeOpF(context, (op1, op2) =>
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{
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return EmitSse2VectorMaxMinOpF(context, op1, op2, isMax: isMaxNum);
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}, scalar: scalar, op1, op2);
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}, scalar: scalar, nCopy, mCopy);
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if (n != null || m != null)
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@ -1189,6 +1189,39 @@ namespace ARMeilleure.Instructions
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}
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}
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[Flags]
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public enum Mxcsr
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{
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Ftz = 1 << 15, // Flush To Zero.
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Um = 1 << 11, // Underflow Mask.
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Dm = 1 << 8, // Denormal Mask.
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Daz = 1 << 6 // Denormals Are Zero.
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}
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public static void EmitSseOrAvxEnterFtzAndDazModesOpF(ArmEmitterContext context, out Operand isTrue)
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{
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isTrue = context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpcrFz)));
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Operand lblTrue = Label();
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context.BranchIfFalse(lblTrue, isTrue);
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context.AddIntrinsicNoRet(Intrinsic.X86Mxcsrmb, Const((int)(Mxcsr.Ftz | Mxcsr.Um | Mxcsr.Dm | Mxcsr.Daz)));
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context.MarkLabel(lblTrue);
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}
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public static void EmitSseOrAvxExitFtzAndDazModesOpF(ArmEmitterContext context, Operand isTrue = null)
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{
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isTrue ??= context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpcrFz)));
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Operand lblTrue = Label();
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context.BranchIfFalse(lblTrue, isTrue);
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context.AddIntrinsicNoRet(Intrinsic.X86Mxcsrub, Const((int)(Mxcsr.Ftz | Mxcsr.Daz)));
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context.MarkLabel(lblTrue);
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}
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public enum CmpCondition
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{
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// Legacy Sse.
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@ -78,6 +78,11 @@ namespace ARMeilleure.Instructions
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return (ulong)GetContext().Fpcr;
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}
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public static bool GetFpcrFz()
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{
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return (GetContext().Fpcr & FPCR.Fz) != 0;
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}
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public static ulong GetFpsr()
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{
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return (ulong)GetContext().Fpsr;
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@ -85,7 +90,7 @@ namespace ARMeilleure.Instructions
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public static uint GetFpscr()
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{
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var context = GetContext();
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ExecutionContext context = GetContext();
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return (uint)(context.Fpsr & FPSR.A32Mask & ~FPSR.Nzcv) |
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(uint)(context.Fpcr & FPCR.A32Mask);
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@ -143,7 +148,7 @@ namespace ARMeilleure.Instructions
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public static void SetFpscr(uint fpscr)
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{
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var context = GetContext();
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ExecutionContext context = GetContext();
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|
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context.Fpsr = FPSR.A32Mask & (FPSR)fpscr;
|
||||
context.Fpcr = FPCR.A32Mask & (FPCR)fpscr;
|
||||
@ -250,7 +255,7 @@ namespace ARMeilleure.Instructions
|
||||
{
|
||||
Statistics.PauseTimer();
|
||||
|
||||
var context = GetContext();
|
||||
ExecutionContext context = GetContext();
|
||||
|
||||
context.CheckInterrupt();
|
||||
|
||||
|
@ -65,6 +65,8 @@ namespace ARMeilleure.IntermediateRepresentation
|
||||
X86Mulps,
|
||||
X86Mulsd,
|
||||
X86Mulss,
|
||||
X86Mxcsrmb,
|
||||
X86Mxcsrub,
|
||||
X86Paddb,
|
||||
X86Paddd,
|
||||
X86Paddq,
|
||||
|
@ -109,6 +109,7 @@ namespace ARMeilleure.Translation
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCtrEl0)));
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetDczidEl0)));
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpcr)));
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpcrFz)));
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpscr))); // A32 only.
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpsr)));
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFunctionAddress)));
|
||||
|
@ -573,6 +573,11 @@ namespace ARMeilleure.Translation
|
||||
return Add(intrin, Local(OperandType.I64), args);
|
||||
}
|
||||
|
||||
public void AddIntrinsicNoRet(Intrinsic intrin, params Operand[] args)
|
||||
{
|
||||
Add(intrin, null, args);
|
||||
}
|
||||
|
||||
private Operand Add(Intrinsic intrin, Operand dest, params Operand[] sources)
|
||||
{
|
||||
NewNextBlockIfNeeded();
|
||||
|
@ -21,7 +21,7 @@ namespace ARMeilleure.Translation.PTC
|
||||
{
|
||||
private const string HeaderMagic = "PTChd";
|
||||
|
||||
private const int InternalVersion = 1758; //! To be incremented manually for each change to the ARMeilleure project.
|
||||
private const int InternalVersion = 1631; //! To be incremented manually for each change to the ARMeilleure project.
|
||||
|
||||
private const string ActualDir = "0";
|
||||
private const string BackupDir = "1";
|
||||
|
@ -17,8 +17,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
protected const ulong CodeBaseAddress = 0x1000;
|
||||
protected const ulong DataBaseAddress = CodeBaseAddress + Size;
|
||||
|
||||
private const bool Ignore_FpcrFz_FpcrDn = false;
|
||||
private const bool IgnoreAllExcept_FpsrQc = false;
|
||||
private static bool Ignore_FpcrFz = false;
|
||||
private static bool Ignore_FpcrDn = false;
|
||||
|
||||
private static bool IgnoreAllExcept_FpsrQc = false;
|
||||
|
||||
private ulong _currAddress;
|
||||
|
||||
@ -205,11 +207,14 @@ namespace Ryujinx.Tests.Cpu
|
||||
int fpsr = 0,
|
||||
bool runUnicorn = true)
|
||||
{
|
||||
if (Ignore_FpcrFz_FpcrDn)
|
||||
if (Ignore_FpcrFz)
|
||||
{
|
||||
#pragma warning disable CS0162
|
||||
fpcr &= ~((1 << (int)Fpcr.Fz) | (1 << (int)Fpcr.Dn));
|
||||
#pragma warning restore CS0162
|
||||
fpcr &= ~(1 << (int)Fpcr.Fz);
|
||||
}
|
||||
|
||||
if (Ignore_FpcrDn)
|
||||
{
|
||||
fpcr &= ~(1 << (int)Fpcr.Dn);
|
||||
}
|
||||
|
||||
Opcode(opcode);
|
||||
@ -323,9 +328,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
if (IgnoreAllExcept_FpsrQc)
|
||||
{
|
||||
#pragma warning disable CS0162
|
||||
fpsrMask &= Fpsr.Qc;
|
||||
#pragma warning restore CS0162
|
||||
}
|
||||
|
||||
if (fpSkips != FpSkips.None)
|
||||
|
Loading…
Reference in New Issue
Block a user