mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-09-10 13:43:17 +02:00
Implement remaining shader double-precision instructions (#2845)
* Implement remaining shader double-precision instructions * Shader cache version bump
This commit is contained in:
parent
a0aa87366c
commit
650cc41c02
@ -40,7 +40,7 @@ namespace Ryujinx.Graphics.Gpu.Shader
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/// <summary>
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/// Version of the codegen (to be changed when codegen or guest format change).
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/// </summary>
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private const ulong ShaderCodeGenVersion = 2876;
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private const ulong ShaderCodeGenVersion = 2845;
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// Progress reporting helpers
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private volatile int _shaderCount;
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@ -35,8 +35,16 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
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VariableType type = GetSrcVarType(operation.Inst, 0);
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string srcExpr = GetSoureExpr(context, src, type);
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string zero;
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NumberFormatter.TryFormat(0, type, out string zero);
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if (type == VariableType.F64)
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{
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zero = "0.0";
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}
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else
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{
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NumberFormatter.TryFormat(0, type, out zero);
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}
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// Starting in the 496.13 NVIDIA driver, there's an issue with assigning variables to negated expressions.
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// (-expr) does not work, but (0.0 - expr) does. This should be removed once the issue is resolved.
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@ -10,7 +10,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
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public static bool TryFormat(int value, VariableType dstType, out string formatted)
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{
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if (dstType == VariableType.F32 || dstType == VariableType.F64)
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if (dstType == VariableType.F32)
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{
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return TryFormatFloat(BitConverter.Int32BitsToSingle(value), out formatted);
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}
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@ -75,69 +75,6 @@ namespace Ryujinx.Graphics.Shader.Instructions
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context.Config.GpuAccessor.Log("Shader instruction Cs2r is not implemented.");
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}
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public static void DmnmxR(EmitterContext context)
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{
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InstDmnmxR op = context.GetOp<InstDmnmxR>();
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context.Config.GpuAccessor.Log("Shader instruction DmnmxR is not implemented.");
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}
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public static void DmnmxI(EmitterContext context)
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{
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InstDmnmxI op = context.GetOp<InstDmnmxI>();
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context.Config.GpuAccessor.Log("Shader instruction DmnmxI is not implemented.");
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}
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public static void DmnmxC(EmitterContext context)
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{
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InstDmnmxC op = context.GetOp<InstDmnmxC>();
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context.Config.GpuAccessor.Log("Shader instruction DmnmxC is not implemented.");
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}
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public static void DsetR(EmitterContext context)
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{
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InstDsetR op = context.GetOp<InstDsetR>();
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context.Config.GpuAccessor.Log("Shader instruction DsetR is not implemented.");
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}
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public static void DsetI(EmitterContext context)
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{
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InstDsetI op = context.GetOp<InstDsetI>();
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context.Config.GpuAccessor.Log("Shader instruction DsetI is not implemented.");
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}
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public static void DsetC(EmitterContext context)
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{
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InstDsetC op = context.GetOp<InstDsetC>();
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context.Config.GpuAccessor.Log("Shader instruction DsetC is not implemented.");
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}
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public static void DsetpR(EmitterContext context)
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{
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InstDsetpR op = context.GetOp<InstDsetpR>();
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context.Config.GpuAccessor.Log("Shader instruction DsetpR is not implemented.");
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}
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public static void DsetpI(EmitterContext context)
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{
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InstDsetpI op = context.GetOp<InstDsetpI>();
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context.Config.GpuAccessor.Log("Shader instruction DsetpI is not implemented.");
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}
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public static void DsetpC(EmitterContext context)
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{
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InstDsetpC op = context.GetOp<InstDsetpC>();
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context.Config.GpuAccessor.Log("Shader instruction DsetpC is not implemented.");
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}
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public static void FchkR(EmitterContext context)
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{
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InstFchkR op = context.GetOp<InstFchkR>();
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@ -98,7 +98,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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var src = GetSrcReg(context, op.SrcB);
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EmitI2I(context, op.ISrcFmt, op.IDstFmt, src, op.ByteSel, op.Dest, op.AbsB, op.NegB, op.Sat);
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EmitI2I(context, op.ISrcFmt, op.IDstFmt, src, op.ByteSel, op.Dest, op.AbsB, op.NegB, op.Sat, op.WriteCC);
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}
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public static void I2iI(EmitterContext context)
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@ -107,7 +107,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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var src = GetSrcImm(context, Imm20ToSInt(op.Imm20));
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EmitI2I(context, op.ISrcFmt, op.IDstFmt, src, op.ByteSel, op.Dest, op.AbsB, op.NegB, op.Sat);
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EmitI2I(context, op.ISrcFmt, op.IDstFmt, src, op.ByteSel, op.Dest, op.AbsB, op.NegB, op.Sat, op.WriteCC);
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}
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public static void I2iC(EmitterContext context)
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@ -116,7 +116,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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var src = GetSrcCbuf(context, op.CbufSlot, op.CbufOffset);
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EmitI2I(context, op.ISrcFmt, op.IDstFmt, src, op.ByteSel, op.Dest, op.AbsB, op.NegB, op.Sat);
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EmitI2I(context, op.ISrcFmt, op.IDstFmt, src, op.ByteSel, op.Dest, op.AbsB, op.NegB, op.Sat, op.WriteCC);
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}
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private static void EmitF2F(
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@ -176,7 +176,6 @@ namespace Ryujinx.Graphics.Shader.Instructions
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if (dstType == IDstFmt.U64)
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{
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context.Config.GpuAccessor.Log("Unimplemented 64-bits F2I.");
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return;
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}
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Instruction fpType = srcType.ToInstFPType();
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@ -198,7 +197,9 @@ namespace Ryujinx.Graphics.Shader.Instructions
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if (!isSignedInt)
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{
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// Negative float to uint cast is undefined, so we clamp the value before conversion.
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srcB = context.FPMaximum(srcB, ConstF(0), fpType);
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Operand c0 = srcType == DstFmt.F64 ? context.PackDouble2x32(0.0) : ConstF(0);
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srcB = context.FPMaximum(srcB, c0, fpType);
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}
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if (srcType == DstFmt.F64)
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@ -292,7 +293,8 @@ namespace Ryujinx.Graphics.Shader.Instructions
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int rd,
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bool absolute,
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bool negate,
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bool saturate)
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bool saturate,
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bool writeCC)
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{
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if ((srcType & ~ISrcDstFmt.S8) > ISrcDstFmt.U32 || (dstType & ~ISrcDstFmt.S8) > ISrcDstFmt.U32)
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{
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@ -337,7 +339,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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context.Copy(GetDest(rd), src);
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// TODO: CC.
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SetZnFlags(context, src, writeCC);
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}
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private static Operand UnpackReg(EmitterContext context, DstFmt floatType, bool h, int reg)
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@ -528,18 +528,5 @@ namespace Ryujinx.Graphics.Shader.Instructions
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context.Copy(GetDest(rd), GetHalfPacked(context, swizzle, res, rd));
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}
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private static void SetDest(EmitterContext context, Operand value, int rd, bool isFP64)
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{
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if (isFP64)
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{
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context.Copy(GetDest(rd), context.UnpackDouble2x32Low(value));
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context.Copy(GetDest2(rd), context.UnpackDouble2x32High(value));
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}
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else
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{
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context.Copy(GetDest(rd), value);
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}
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}
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}
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}
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@ -11,6 +11,156 @@ namespace Ryujinx.Graphics.Shader.Instructions
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{
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static partial class InstEmit
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{
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public static void DsetR(EmitterContext context)
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{
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InstDsetR op = context.GetOp<InstDsetR>();
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var srcA = GetSrcReg(context, op.SrcA, isFP64: true);
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var srcB = GetSrcReg(context, op.SrcB, isFP64: true);
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EmitFset(
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context,
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op.FComp,
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op.Bop,
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srcA,
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srcB,
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op.SrcPred,
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op.SrcPredInv,
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op.Dest,
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op.AbsA,
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op.AbsB,
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op.NegA,
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op.NegB,
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op.BVal,
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op.WriteCC,
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isFP64: true);
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}
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public static void DsetI(EmitterContext context)
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{
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InstDsetI op = context.GetOp<InstDsetI>();
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var srcA = GetSrcReg(context, op.SrcA, isFP64: true);
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var srcB = GetSrcImm(context, Imm20ToFloat(op.Imm20), isFP64: true);
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EmitFset(
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context,
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op.FComp,
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op.Bop,
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srcA,
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srcB,
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op.SrcPred,
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op.SrcPredInv,
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op.Dest,
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op.AbsA,
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op.AbsB,
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op.NegA,
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op.NegB,
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op.BVal,
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op.WriteCC,
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isFP64: true);
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}
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public static void DsetC(EmitterContext context)
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{
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InstDsetC op = context.GetOp<InstDsetC>();
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var srcA = GetSrcReg(context, op.SrcA, isFP64: true);
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var srcB = GetSrcCbuf(context, op.CbufSlot, op.CbufOffset, isFP64: true);
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EmitFset(
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context,
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op.FComp,
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op.Bop,
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srcA,
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srcB,
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op.SrcPred,
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op.SrcPredInv,
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op.Dest,
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op.AbsA,
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op.AbsB,
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op.NegA,
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op.NegB,
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op.BVal,
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op.WriteCC,
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isFP64: true);
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}
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public static void DsetpR(EmitterContext context)
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{
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InstDsetpR op = context.GetOp<InstDsetpR>();
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var srcA = GetSrcReg(context, op.SrcA, isFP64: true);
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var srcB = GetSrcReg(context, op.SrcB, isFP64: true);
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EmitFsetp(
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context,
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op.FComp,
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op.Bop,
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srcA,
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srcB,
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op.SrcPred,
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op.SrcPredInv,
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op.DestPred,
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op.DestPredInv,
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op.AbsA,
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op.AbsB,
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op.NegA,
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op.NegB,
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writeCC: false,
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isFP64: true);
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}
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public static void DsetpI(EmitterContext context)
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{
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InstDsetpI op = context.GetOp<InstDsetpI>();
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var srcA = GetSrcReg(context, op.SrcA, isFP64: true);
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var srcB = GetSrcImm(context, Imm20ToFloat(op.Imm20), isFP64: true);
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EmitFsetp(
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context,
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op.FComp,
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op.Bop,
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srcA,
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srcB,
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op.SrcPred,
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op.SrcPredInv,
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op.DestPred,
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op.DestPredInv,
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op.AbsA,
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op.AbsB,
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op.NegA,
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op.NegB,
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writeCC: false,
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isFP64: true);
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}
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public static void DsetpC(EmitterContext context)
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{
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InstDsetpC op = context.GetOp<InstDsetpC>();
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var srcA = GetSrcReg(context, op.SrcA, isFP64: true);
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var srcB = GetSrcCbuf(context, op.CbufSlot, op.CbufOffset, isFP64: true);
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EmitFsetp(
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context,
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op.FComp,
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op.Bop,
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srcA,
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srcB,
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op.SrcPred,
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op.SrcPredInv,
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op.DestPred,
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op.DestPredInv,
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op.AbsA,
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op.AbsB,
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op.NegA,
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op.NegB,
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writeCC: false,
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isFP64: true);
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}
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public static void FcmpR(EmitterContext context)
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{
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InstFcmpR op = context.GetOp<InstFcmpR>();
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@ -240,12 +390,15 @@ namespace Ryujinx.Graphics.Shader.Instructions
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bool negateA,
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bool negateB,
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bool boolFloat,
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bool writeCC)
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bool writeCC,
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bool isFP64 = false)
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{
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srcA = context.FPAbsNeg(srcA, absoluteA, negateA);
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srcB = context.FPAbsNeg(srcB, absoluteB, negateB);
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Instruction fpType = isFP64 ? Instruction.FP64 : Instruction.FP32;
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Operand res = GetFPComparison(context, cmpOp, srcA, srcB);
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srcA = context.FPAbsNeg(srcA, absoluteA, negateA, fpType);
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srcB = context.FPAbsNeg(srcB, absoluteB, negateB, fpType);
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Operand res = GetFPComparison(context, cmpOp, srcA, srcB, fpType);
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Operand pred = GetPredicate(context, srcPred, srcPredInv);
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res = GetPredLogicalOp(context, logicOp, res, pred);
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@ -282,12 +435,15 @@ namespace Ryujinx.Graphics.Shader.Instructions
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bool absoluteB,
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bool negateA,
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bool negateB,
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bool writeCC)
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bool writeCC,
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bool isFP64 = false)
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{
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srcA = context.FPAbsNeg(srcA, absoluteA, negateA);
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srcB = context.FPAbsNeg(srcB, absoluteB, negateB);
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Instruction fpType = isFP64 ? Instruction.FP64 : Instruction.FP32;
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Operand p0Res = GetFPComparison(context, cmpOp, srcA, srcB);
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srcA = context.FPAbsNeg(srcA, absoluteA, negateA, fpType);
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srcB = context.FPAbsNeg(srcB, absoluteB, negateB, fpType);
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Operand p0Res = GetFPComparison(context, cmpOp, srcA, srcB, fpType);
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Operand p1Res = context.BitwiseNot(p0Res);
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Operand pred = GetPredicate(context, srcPred, srcPredInv);
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@ -367,7 +523,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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context.Copy(Register(destPredInv, RegisterType.Predicate), p1Res);
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}
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private static Operand GetFPComparison(EmitterContext context, FComp cond, Operand srcA, Operand srcB)
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private static Operand GetFPComparison(EmitterContext context, FComp cond, Operand srcA, Operand srcB, Instruction fpType = Instruction.FP32)
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{
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Operand res;
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@ -381,7 +537,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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}
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else if (cond == FComp.Nan || cond == FComp.Num)
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{
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res = context.BitwiseOr(context.IsNan(srcA), context.IsNan(srcB));
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res = context.BitwiseOr(context.IsNan(srcA, fpType), context.IsNan(srcB, fpType));
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if (cond == FComp.Num)
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{
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@ -404,12 +560,12 @@ namespace Ryujinx.Graphics.Shader.Instructions
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default: throw new ArgumentException($"Unexpected condition \"{cond}\".");
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}
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res = context.Add(inst | Instruction.FP32, Local(), srcA, srcB);
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res = context.Add(inst | fpType, Local(), srcA, srcB);
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if ((cond & FComp.Nan) != 0)
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{
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res = context.BitwiseOr(res, context.IsNan(srcA));
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res = context.BitwiseOr(res, context.IsNan(srcB));
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res = context.BitwiseOr(res, context.IsNan(srcA, fpType));
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res = context.BitwiseOr(res, context.IsNan(srcB, fpType));
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}
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}
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@ -9,6 +9,39 @@ namespace Ryujinx.Graphics.Shader.Instructions
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{
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static partial class InstEmit
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{
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public static void DmnmxR(EmitterContext context)
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{
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InstDmnmxR op = context.GetOp<InstDmnmxR>();
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var srcA = GetSrcReg(context, op.SrcA, isFP64: true);
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var srcB = GetSrcReg(context, op.SrcB, isFP64: true);
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var srcPred = GetPredicate(context, op.SrcPred, op.SrcPredInv);
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EmitFmnmx(context, srcA, srcB, srcPred, op.Dest, op.AbsA, op.AbsB, op.NegA, op.NegB, op.WriteCC, isFP64: true);
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}
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public static void DmnmxI(EmitterContext context)
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{
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InstDmnmxI op = context.GetOp<InstDmnmxI>();
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var srcA = GetSrcReg(context, op.SrcA, isFP64: true);
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var srcB = GetSrcImm(context, Imm20ToFloat(op.Imm20), isFP64: true);
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var srcPred = GetPredicate(context, op.SrcPred, op.SrcPredInv);
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EmitFmnmx(context, srcA, srcB, srcPred, op.Dest, op.AbsA, op.AbsB, op.NegA, op.NegB, op.WriteCC, isFP64: true);
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}
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public static void DmnmxC(EmitterContext context)
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{
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InstDmnmxC op = context.GetOp<InstDmnmxC>();
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var srcA = GetSrcReg(context, op.SrcA, isFP64: true);
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var srcB = GetSrcCbuf(context, op.CbufSlot, op.CbufOffset, isFP64: true);
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var srcPred = GetPredicate(context, op.SrcPred, op.SrcPredInv);
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|
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EmitFmnmx(context, srcA, srcB, srcPred, op.Dest, op.AbsA, op.AbsB, op.NegA, op.NegB, op.WriteCC, isFP64: true);
|
||||
}
|
||||
|
||||
public static void FmnmxR(EmitterContext context)
|
||||
{
|
||||
InstFmnmxR op = context.GetOp<InstFmnmxR>();
|
||||
@ -52,19 +85,22 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
||||
bool absoluteB,
|
||||
bool negateA,
|
||||
bool negateB,
|
||||
bool writeCC)
|
||||
bool writeCC,
|
||||
bool isFP64 = false)
|
||||
{
|
||||
srcA = context.FPAbsNeg(srcA, absoluteA, negateA);
|
||||
srcB = context.FPAbsNeg(srcB, absoluteB, negateB);
|
||||
Instruction fpType = isFP64 ? Instruction.FP64 : Instruction.FP32;
|
||||
|
||||
Operand resMin = context.FPMinimum(srcA, srcB);
|
||||
Operand resMax = context.FPMaximum(srcA, srcB);
|
||||
srcA = context.FPAbsNeg(srcA, absoluteA, negateA, fpType);
|
||||
srcB = context.FPAbsNeg(srcB, absoluteB, negateB, fpType);
|
||||
|
||||
Operand dest = GetDest(rd);
|
||||
Operand resMin = context.FPMinimum(srcA, srcB, fpType);
|
||||
Operand resMax = context.FPMaximum(srcA, srcB, fpType);
|
||||
|
||||
context.Copy(dest, context.ConditionalSelect(srcPred, resMin, resMax));
|
||||
Operand res = context.ConditionalSelect(srcPred, resMin, resMax);
|
||||
|
||||
SetFPZnFlags(context, dest, writeCC);
|
||||
SetDest(context, res, rd, isFP64);
|
||||
|
||||
SetFPZnFlags(context, res, writeCC, fpType);
|
||||
}
|
||||
}
|
||||
}
|
@ -58,7 +58,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
||||
{
|
||||
if (isFP64)
|
||||
{
|
||||
return context.FP32ConvertToFP64(Const(imm));
|
||||
return context.PackDouble2x32(Const(0), Const(imm));
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -218,6 +218,19 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
||||
return local;
|
||||
}
|
||||
|
||||
public static void SetDest(EmitterContext context, Operand value, int rd, bool isFP64)
|
||||
{
|
||||
if (isFP64)
|
||||
{
|
||||
context.Copy(GetDest(rd), context.UnpackDouble2x32Low(value));
|
||||
context.Copy(GetDest2(rd), context.UnpackDouble2x32High(value));
|
||||
}
|
||||
else
|
||||
{
|
||||
context.Copy(GetDest(rd), value);
|
||||
}
|
||||
}
|
||||
|
||||
public static int Imm16ToSInt(int imm16)
|
||||
{
|
||||
return (short)imm16;
|
||||
|
@ -61,11 +61,23 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
||||
res = context.FPReciprocalSquareRoot(res);
|
||||
break;
|
||||
|
||||
case MufuOp.Rcp64h:
|
||||
res = context.PackDouble2x32(OperandHelper.Const(0), res);
|
||||
res = context.UnpackDouble2x32High(context.FPReciprocal(res, Instruction.FP64));
|
||||
break;
|
||||
|
||||
case MufuOp.Rsq64h:
|
||||
res = context.PackDouble2x32(OperandHelper.Const(0), res);
|
||||
res = context.UnpackDouble2x32High(context.FPReciprocalSquareRoot(res, Instruction.FP64));
|
||||
break;
|
||||
|
||||
case MufuOp.Sqrt:
|
||||
res = context.FPSquareRoot(res);
|
||||
break;
|
||||
|
||||
default: /* TODO */ break;
|
||||
default:
|
||||
context.Config.GpuAccessor.Log($"Invalid MUFU operation \"{op.MufuOp}\".");
|
||||
break;
|
||||
}
|
||||
|
||||
context.Copy(GetDest(op.Dest), context.FPSaturate(res, op.Sat));
|
||||
|
@ -87,7 +87,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr
|
||||
Add(Instruction.ImageLoad, VariableType.F32);
|
||||
Add(Instruction.ImageStore, VariableType.None);
|
||||
Add(Instruction.ImageAtomic, VariableType.S32);
|
||||
Add(Instruction.IsNan, VariableType.Bool, VariableType.F32);
|
||||
Add(Instruction.IsNan, VariableType.Bool, VariableType.Scalar);
|
||||
Add(Instruction.LoadAttribute, VariableType.F32, VariableType.S32, VariableType.S32, VariableType.S32);
|
||||
Add(Instruction.LoadConstant, VariableType.F32, VariableType.S32, VariableType.S32);
|
||||
Add(Instruction.LoadGlobal, VariableType.U32, VariableType.S32, VariableType.S32);
|
||||
|
@ -1,4 +1,5 @@
|
||||
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
||||
using System;
|
||||
|
||||
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
||||
|
||||
@ -271,9 +272,9 @@ namespace Ryujinx.Graphics.Shader.Translation
|
||||
return context.Add(Instruction.FP32 | Instruction.Cosine, Local(), a);
|
||||
}
|
||||
|
||||
public static Operand FPDivide(this EmitterContext context, Operand a, Operand b)
|
||||
public static Operand FPDivide(this EmitterContext context, Operand a, Operand b, Instruction fpType = Instruction.FP32)
|
||||
{
|
||||
return context.Add(Instruction.FP32 | Instruction.Divide, Local(), a, b);
|
||||
return context.Add(fpType | Instruction.Divide, Local(), a, b);
|
||||
}
|
||||
|
||||
public static Operand FPExponentB2(this EmitterContext context, Operand a)
|
||||
@ -301,9 +302,9 @@ namespace Ryujinx.Graphics.Shader.Translation
|
||||
return context.Add(fpType | Instruction.Maximum, Local(), a, b);
|
||||
}
|
||||
|
||||
public static Operand FPMinimum(this EmitterContext context, Operand a, Operand b)
|
||||
public static Operand FPMinimum(this EmitterContext context, Operand a, Operand b, Instruction fpType = Instruction.FP32)
|
||||
{
|
||||
return context.Add(Instruction.FP32 | Instruction.Minimum, Local(), a, b);
|
||||
return context.Add(fpType | Instruction.Minimum, Local(), a, b);
|
||||
}
|
||||
|
||||
public static Operand FPMultiply(this EmitterContext context, Operand a, Operand b, Instruction fpType = Instruction.FP32)
|
||||
@ -326,14 +327,14 @@ namespace Ryujinx.Graphics.Shader.Translation
|
||||
return context.Add(fpType | Instruction.Negate, Local(), a);
|
||||
}
|
||||
|
||||
public static Operand FPReciprocal(this EmitterContext context, Operand a)
|
||||
public static Operand FPReciprocal(this EmitterContext context, Operand a, Instruction fpType = Instruction.FP32)
|
||||
{
|
||||
return context.FPDivide(ConstF(1), a);
|
||||
return context.FPDivide(fpType == Instruction.FP64 ? context.PackDouble2x32(1.0) : ConstF(1), a, fpType);
|
||||
}
|
||||
|
||||
public static Operand FPReciprocalSquareRoot(this EmitterContext context, Operand a)
|
||||
public static Operand FPReciprocalSquareRoot(this EmitterContext context, Operand a, Instruction fpType = Instruction.FP32)
|
||||
{
|
||||
return context.Add(Instruction.FP32 | Instruction.ReciprocalSquareRoot, Local(), a);
|
||||
return context.Add(fpType | Instruction.ReciprocalSquareRoot, Local(), a);
|
||||
}
|
||||
|
||||
public static Operand FPRound(this EmitterContext context, Operand a, Instruction fpType = Instruction.FP32)
|
||||
@ -353,7 +354,9 @@ namespace Ryujinx.Graphics.Shader.Translation
|
||||
|
||||
public static Operand FPSaturate(this EmitterContext context, Operand a, Instruction fpType = Instruction.FP32)
|
||||
{
|
||||
return context.Add(fpType | Instruction.Clamp, Local(), a, ConstF(0), ConstF(1));
|
||||
return fpType == Instruction.FP64
|
||||
? context.Add(fpType | Instruction.Clamp, Local(), a, context.PackDouble2x32(0.0), context.PackDouble2x32(1.0))
|
||||
: context.Add(fpType | Instruction.Clamp, Local(), a, ConstF(0), ConstF(1));
|
||||
}
|
||||
|
||||
public static Operand FPSine(this EmitterContext context, Operand a)
|
||||
@ -541,9 +544,9 @@ namespace Ryujinx.Graphics.Shader.Translation
|
||||
return context.Add(Instruction.Subtract, Local(), a, b);
|
||||
}
|
||||
|
||||
public static Operand IsNan(this EmitterContext context, Operand a)
|
||||
public static Operand IsNan(this EmitterContext context, Operand a, Instruction fpType = Instruction.FP32)
|
||||
{
|
||||
return context.Add(Instruction.IsNan, Local(), a);
|
||||
return context.Add(fpType | Instruction.IsNan, Local(), a);
|
||||
}
|
||||
|
||||
public static Operand LoadAttribute(this EmitterContext context, Operand a, Operand b, Operand c)
|
||||
@ -595,6 +598,13 @@ namespace Ryujinx.Graphics.Shader.Translation
|
||||
return context.Add(Instruction.MultiplyHighU32, Local(), a, b);
|
||||
}
|
||||
|
||||
public static Operand PackDouble2x32(this EmitterContext context, double value)
|
||||
{
|
||||
long valueAsLong = BitConverter.DoubleToInt64Bits(value);
|
||||
|
||||
return context.Add(Instruction.PackDouble2x32, Local(), Const((int)valueAsLong), Const((int)(valueAsLong >> 32)));
|
||||
}
|
||||
|
||||
public static Operand PackDouble2x32(this EmitterContext context, Operand a, Operand b)
|
||||
{
|
||||
return context.Add(Instruction.PackDouble2x32, Local(), a, b);
|
||||
|
Loading…
Reference in New Issue
Block a user