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Add BIT instruction
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19b8344568
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@ -141,6 +141,7 @@ namespace ChocolArm64
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Set("0x001110011xxxxx000111xxxxxxxxxx", AInstEmit.Bic_V, typeof(AOpCodeSimdReg));
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Set("0x10111100000xxx<<x101xxxxxxxxxx", AInstEmit.Bic_Vi, typeof(AOpCodeSimdImm));
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Set("0x101110111xxxxx000111xxxxxxxxxx", AInstEmit.Bif_V, typeof(AOpCodeSimdReg));
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Set("0x101110101xxxxx000111xxxxxxxxxx", AInstEmit.Bit_V, typeof(AOpCodeSimdReg));
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Set("0x101110011xxxxx000111xxxxxxxxxx", AInstEmit.Bsl_V, typeof(AOpCodeSimdReg));
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Set("0>101110<<1xxxxx100011xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimdReg));
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Set("0>001110<<100000100110xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimd));
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@ -33,6 +33,16 @@ namespace ChocolArm64.Instruction
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}
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public static void Bif_V(AILEmitterCtx Context)
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{
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EmitBitBif(Context, true);
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}
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public static void Bit_V(AILEmitterCtx Context)
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{
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EmitBitBif(Context, false);
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}
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public static void EmitBitBif(AILEmitterCtx Context, bool NotRm)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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@ -47,6 +57,11 @@ namespace ChocolArm64.Instruction
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EmitVectorExtractZx(Context, Op.Rm, Index, Op.Size);
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if (NotRm)
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{
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Context.Emit(OpCodes.Not);
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}
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Context.Emit(OpCodes.And);
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EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size);
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