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CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390)
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ARMeilleure/Decoders/OpCode32SimdRegWide.cs
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17
ARMeilleure/Decoders/OpCode32SimdRegWide.cs
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@ -0,0 +1,17 @@
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namespace ARMeilleure.Decoders
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{
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sealed class OpCode32SimdRegWide : OpCode32SimdReg
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{
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public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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Q = false;
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RegisterSize = RegisterSize.Simd64;
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// Subclasses have their own handling of Vx to account for before checking.
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if (GetType() == typeof(OpCode32SimdRegWide) && DecoderHelper.VectorArgumentsInvalid(true, Vd, Vn))
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{
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Instruction = InstDescriptor.Undefined;
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}
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}
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}
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}
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@ -803,6 +803,7 @@ namespace ARMeilleure.Decoders
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SetA32("111100100xxxxxxxxxxx1000xxx0xxxx", InstName.Vadd, InstEmit32.Vadd_I, typeof(OpCode32SimdReg));
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SetA32("<<<<11100x11xxxxxxxx101xx0x0xxxx", InstName.Vadd, InstEmit32.Vadd_S, typeof(OpCode32SimdRegS));
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SetA32("111100100x00xxxxxxxx1101xxx0xxxx", InstName.Vadd, InstEmit32.Vadd_V, typeof(OpCode32SimdReg));
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SetA32("1111001x1x<<xxxxxxxx0001x0x0xxxx", InstName.Vaddw, InstEmit32.Vaddw_I, typeof(OpCode32SimdRegWide));
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SetA32("111100100x00xxxxxxxx0001xxx1xxxx", InstName.Vand, InstEmit32.Vand_I, typeof(OpCode32SimdBinary));
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SetA32("111100110x11xxxxxxxx0001xxx1xxxx", InstName.Vbif, InstEmit32.Vbif, typeof(OpCode32SimdBinary));
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SetA32("111100110x10xxxxxxxx0001xxx1xxxx", InstName.Vbit, InstEmit32.Vbit, typeof(OpCode32SimdBinary));
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@ -946,6 +947,7 @@ namespace ARMeilleure.Decoders
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SetA32("111100110xxxxxxxxxxx1000xxx0xxxx", InstName.Vsub, InstEmit32.Vsub_I, typeof(OpCode32SimdReg));
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SetA32("<<<<11100x11xxxxxxxx101xx1x0xxxx", InstName.Vsub, InstEmit32.Vsub_S, typeof(OpCode32SimdRegS));
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SetA32("111100100x10xxxxxxxx1101xxx0xxxx", InstName.Vsub, InstEmit32.Vsub_V, typeof(OpCode32SimdReg));
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SetA32("1111001x1x<<xxxxxxxx0011x0x0xxxx", InstName.Vsubw, InstEmit32.Vsubw_I, typeof(OpCode32SimdRegWide));
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SetA32("111100111x11xxxxxxxx10xxxxx0xxxx", InstName.Vtbl, InstEmit32.Vtbl, typeof(OpCode32SimdTbl));
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SetA32("111100111x11<<10xxxx00001xx0xxxx", InstName.Vtrn, InstEmit32.Vtrn, typeof(OpCode32SimdCmpZ));
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SetA32("111100111x11<<10xxxx00010xx0xxxx", InstName.Vuzp, InstEmit32.Vuzp, typeof(OpCode32SimdCmpZ));
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@ -107,6 +107,13 @@ namespace ARMeilleure.Instructions
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}
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}
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public static void Vaddw_I(ArmEmitterContext context)
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{
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OpCode32SimdRegWide op = (OpCode32SimdRegWide)context.CurrOp;
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EmitVectorBinaryWideOpI32(context, (op1, op2) => context.Add(op1, op2), !op.U);
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}
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public static void Vdup(ArmEmitterContext context)
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{
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OpCode32SimdDupGP op = (OpCode32SimdDupGP)context.CurrOp;
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@ -1191,6 +1198,13 @@ namespace ARMeilleure.Instructions
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}
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}
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public static void Vsubw_I(ArmEmitterContext context)
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{
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OpCode32SimdRegWide op = (OpCode32SimdRegWide)context.CurrOp;
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EmitVectorBinaryWideOpI32(context, (op1, op2) => context.Subtract(op1, op2), !op.U);
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}
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private static void EmitSse41MaxMinNumOpF32(ArmEmitterContext context, bool isMaxNum, bool scalar)
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{
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IOpCode32Simd op = (IOpCode32Simd)context.CurrOp;
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@ -281,6 +281,30 @@ namespace ARMeilleure.Instructions
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorBinaryWideOpI32(ArmEmitterContext context, Func2I emit, bool signed)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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Operand res = context.VectorZero();
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size + 1, signed);
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Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed);
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if (op.Size == 2)
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{
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me = signed ? context.SignExtend32(OperandType.I64, me) : context.ZeroExtend32(OperandType.I64, me);
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}
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res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorTernaryLongOpI32(ArmEmitterContext context, Func3I emit, bool signed)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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@ -545,6 +545,7 @@ namespace ARMeilleure.Instructions
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// FP & SIMD (AArch32)
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Vabs,
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Vadd,
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Vaddw,
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Vand,
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Vbif,
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Vbit,
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@ -611,6 +612,7 @@ namespace ARMeilleure.Instructions
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Vrsqrte,
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Vrsqrts,
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Vsub,
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Vsubw,
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Vtbl,
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Vtrn,
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Vuzp,
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@ -20,7 +20,7 @@ namespace ARMeilleure.Translation.PTC
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{
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private const string HeaderMagic = "PTChd";
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private const int InternalVersion = 10; //! To be incremented manually for each change to the ARMeilleure project.
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private const int InternalVersion = 11; //! To be incremented manually for each change to the ARMeilleure project.
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private const string BaseDir = "Ryujinx";
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@ -13,6 +13,15 @@ namespace Ryujinx.Tests.Cpu
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#if SimdReg32
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#region "ValueSource (Opcodes)"
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private static uint[] _V_Add_Sub_Wide_I_()
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{
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return new uint[]
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{
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0xf2800100u, // VADDW.S8 Q0, Q0, D0
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0xf2800300u // VSUBW.S8 Q0, Q0, D0
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};
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}
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private static uint[] _Vp_Add_Max_Min_F_()
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{
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return new uint[]
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@ -38,60 +47,6 @@ namespace Ryujinx.Tests.Cpu
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#endregion
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#region "ValueSource (Types)"
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private static ulong[] _1B1H1S1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x000000000000007Ful,
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0x0000000000000080ul, 0x00000000000000FFul,
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0x0000000000007FFFul, 0x0000000000008000ul,
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0x000000000000FFFFul, 0x000000007FFFFFFFul,
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0x0000000080000000ul, 0x00000000FFFFFFFFul,
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0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul,
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0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _1H1S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x0000000000007FFFul,
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0x0000000000008000ul, 0x000000000000FFFFul,
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0x000000007FFFFFFFul, 0x0000000080000000ul,
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0x00000000FFFFFFFFul };
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}
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private static ulong[] _4H2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _4H2S1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B4H2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B4H2S1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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@ -267,6 +222,40 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void V_Add_Sub_Wide_I([ValueSource("_V_Add_Sub_Wide_I_")] uint opcode,
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[Range(0u, 5u)] uint rd,
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[Range(0u, 5u)] uint rn,
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[Range(0u, 5u)] uint rm,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong a,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong b,
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[Values(0u, 1u, 2u)] uint size, // <SU8, SU16, SU32>
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[Values] bool u) // <S, U>
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{
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if (u)
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{
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opcode |= 1 << 24;
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}
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rd >>= 1; rd <<= 1;
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rn >>= 1; rn <<= 1;
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= (size & 0x3) << 20;
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V128 v0 = MakeVectorE0E1(z, ~z);
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V128 v1 = MakeVectorE0E1(a, ~a);
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V128 v2 = MakeVectorE0E1(b, ~b);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VCMP.f<size> Vd, Vm")]
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public void Vcmp([Values(2u, 3u)] uint size,
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[ValueSource("_1S_F_")] ulong a,
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