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Add MLA (vector by element), fixes some cases of MUL (vector by element)?
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79a5939734
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@ -228,6 +228,7 @@ namespace ChocolArm64
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Set("xx111100x11xxxxxxxxx10xxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeSimdMemReg));
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Set("xx011100xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.LdrLit, typeof(AOpCodeSimdMemLit));
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Set("0x001110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mla_V, typeof(AOpCodeSimdReg));
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Set("0x101111xxxxxxxx0000x0xxxxxxxxxx", AInstEmit.Mla_Ve, typeof(AOpCodeSimdRegElem));
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Set("0x101110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mls_V, typeof(AOpCodeSimdReg));
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Set("0x00111100000xxx0xx001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
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Set("0x00111100000xxx10x001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
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@ -11,9 +11,8 @@ namespace ChocolArm64.Decoder
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switch (Size)
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{
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case 1:
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Index = (OpCode >> 21) & 1 |
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(OpCode >> 10) & 2 |
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(OpCode >> 18) & 4;
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Index = (OpCode >> 20) & 3 |
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(OpCode >> 9) & 4;
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Rm &= 0xf;
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@ -335,6 +335,15 @@ namespace ChocolArm64.Instruction
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});
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}
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public static void Mla_Ve(AILEmitterCtx Context)
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{
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EmitVectorTernaryOpByElemZx(Context, () =>
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{
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Context.Emit(OpCodes.Mul);
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Context.Emit(OpCodes.Add);
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});
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}
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public static void Mls_V(AILEmitterCtx Context)
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{
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EmitVectorTernaryOpZx(Context, () =>
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@ -381,13 +381,16 @@ namespace ChocolArm64.Instruction
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}
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
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EmitVectorExtract(Context, Op.Rm, Index, Op.Size, Signed);
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EmitVectorExtract(Context, Op.Rm, Elem, Op.Size, Signed);
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Emit();
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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EmitVectorInsertTmp(Context, Index, Op.Size);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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