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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload * Add files via upload * Add files via upload * CPE * Add EmitSse42Crc32() * Update CpuTestSimdCmp.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update Instructions.cs
This commit is contained in:
parent
37a6e84fd4
commit
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@ -225,16 +225,16 @@ namespace ChocolArm64
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SetA64("000111100x1xxxxxxxxx01xxxxx0xxxx", AInstEmit.Fccmp_S, typeof(AOpCodeSimdFcond));
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SetA64("000111100x1xxxxxxxxx01xxxxx1xxxx", AInstEmit.Fccmpe_S, typeof(AOpCodeSimdFcond));
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SetA64("010111100x1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmeq_S, typeof(AOpCodeSimdReg));
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SetA64("0>0011100<1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmeq_V, typeof(AOpCodeSimdReg));
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SetA64("010111101x100000110110xxxxxxxxxx", AInstEmit.Fcmeq_S, typeof(AOpCodeSimd));
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SetA64("0>0011100<1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmeq_V, typeof(AOpCodeSimdReg));
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SetA64("0>0011101<100000110110xxxxxxxxxx", AInstEmit.Fcmeq_V, typeof(AOpCodeSimd));
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SetA64("011111100x1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmge_S, typeof(AOpCodeSimdReg));
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SetA64("0>1011100<1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmge_V, typeof(AOpCodeSimdReg));
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SetA64("011111101x100000110010xxxxxxxxxx", AInstEmit.Fcmge_S, typeof(AOpCodeSimd));
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SetA64("0>1011100<1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmge_V, typeof(AOpCodeSimdReg));
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SetA64("0>1011101<100000110010xxxxxxxxxx", AInstEmit.Fcmge_V, typeof(AOpCodeSimd));
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SetA64("011111101x1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmgt_S, typeof(AOpCodeSimdReg));
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SetA64("0>1011101<1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmgt_V, typeof(AOpCodeSimdReg));
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SetA64("010111101x100000110010xxxxxxxxxx", AInstEmit.Fcmgt_S, typeof(AOpCodeSimd));
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SetA64("0>1011101<1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmgt_V, typeof(AOpCodeSimdReg));
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SetA64("0>0011101<100000110010xxxxxxxxxx", AInstEmit.Fcmgt_V, typeof(AOpCodeSimd));
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SetA64("011111101x100000110110xxxxxxxxxx", AInstEmit.Fcmle_S, typeof(AOpCodeSimd));
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SetA64("0>1011101<100000110110xxxxxxxxxx", AInstEmit.Fcmle_V, typeof(AOpCodeSimd));
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@ -6,7 +6,15 @@ public static class AOptimizations
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public static bool GenerateCallStack = true;
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public static bool UseSse2IfAvailable = true;
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private static bool UseAllSseIfAvailable = true;
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internal static bool UseSse2 = UseSse2IfAvailable && Sse2.IsSupported;
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private static bool UseSseIfAvailable = true;
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private static bool UseSse2IfAvailable = true;
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private static bool UseSse41IfAvailable = true;
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private static bool UseSse42IfAvailable = true;
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internal static bool UseSse = (UseAllSseIfAvailable && UseSseIfAvailable) && Sse.IsSupported;
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internal static bool UseSse2 = (UseAllSseIfAvailable && UseSse2IfAvailable) && Sse2.IsSupported;
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internal static bool UseSse41 = (UseAllSseIfAvailable && UseSse41IfAvailable) && Sse41.IsSupported;
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internal static bool UseSse42 = (UseAllSseIfAvailable && UseSse42IfAvailable) && Sse42.IsSupported;
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}
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@ -1,7 +1,9 @@
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using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using System.Runtime.Intrinsics.X86;
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namespace ChocolArm64.Instruction
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{
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@ -29,22 +31,62 @@ namespace ChocolArm64.Instruction
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public static void Crc32cb(AILEmitterCtx Context)
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32cb));
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if (AOptimizations.UseSse42)
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{
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EmitSse42Crc32(Context, typeof(uint), typeof(byte));
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}
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else
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32cb));
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}
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}
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public static void Crc32ch(AILEmitterCtx Context)
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32ch));
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if (AOptimizations.UseSse42)
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{
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EmitSse42Crc32(Context, typeof(uint), typeof(ushort));
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}
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else
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32ch));
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}
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}
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public static void Crc32cw(AILEmitterCtx Context)
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32cw));
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if (AOptimizations.UseSse42)
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{
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EmitSse42Crc32(Context, typeof(uint), typeof(uint));
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}
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else
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32cw));
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}
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}
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public static void Crc32cx(AILEmitterCtx Context)
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32cx));
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if (AOptimizations.UseSse42)
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{
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EmitSse42Crc32(Context, typeof(ulong), typeof(ulong));
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}
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else
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32cx));
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}
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}
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private static void EmitSse42Crc32(AILEmitterCtx Context, Type TCrc, Type TData)
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{
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AOpCodeAluRs Op = (AOpCodeAluRs)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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Context.EmitLdintzr(Op.Rm);
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Context.EmitCall(typeof(Sse42).GetMethod(nameof(Sse42.Crc32), new Type[] { TCrc, TData }));
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Context.EmitStintzr(Op.Rd);
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}
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private static void EmitCrc32(AILEmitterCtx Context, string Name)
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@ -70,4 +112,4 @@ namespace ChocolArm64.Instruction
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Context.EmitStintzr(Op.Rd);
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}
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}
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}
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}
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@ -319,9 +319,9 @@ namespace ChocolArm64.Instruction
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public static void Fadd_S(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2)
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if (AOptimizations.UseSse && AOptimizations.UseSse2)
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{
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EmitSse2CallF(Context, nameof(Sse2.AddScalar));
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EmitSseOrSse2CallF(Context, nameof(Sse.AddScalar));
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}
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else
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{
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@ -331,9 +331,9 @@ namespace ChocolArm64.Instruction
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public static void Fadd_V(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2)
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if (AOptimizations.UseSse && AOptimizations.UseSse2)
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{
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EmitSse2CallF(Context, nameof(Sse2.Add));
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EmitSseOrSse2CallF(Context, nameof(Sse.Add));
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}
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else
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{
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@ -389,9 +389,9 @@ namespace ChocolArm64.Instruction
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public static void Fdiv_S(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2)
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if (AOptimizations.UseSse && AOptimizations.UseSse2)
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{
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EmitSse2CallF(Context, nameof(Sse2.DivideScalar));
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EmitSseOrSse2CallF(Context, nameof(Sse.DivideScalar));
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}
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else
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{
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@ -401,9 +401,9 @@ namespace ChocolArm64.Instruction
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public static void Fdiv_V(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2)
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if (AOptimizations.UseSse && AOptimizations.UseSse2)
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{
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EmitSse2CallF(Context, nameof(Sse2.Divide));
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EmitSseOrSse2CallF(Context, nameof(Sse.Divide));
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}
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else
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{
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@ -563,9 +563,9 @@ namespace ChocolArm64.Instruction
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public static void Fmul_S(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2)
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if (AOptimizations.UseSse && AOptimizations.UseSse2)
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{
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EmitSse2CallF(Context, nameof(Sse2.MultiplyScalar));
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EmitSseOrSse2CallF(Context, nameof(Sse.MultiplyScalar));
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}
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else
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{
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@ -580,9 +580,9 @@ namespace ChocolArm64.Instruction
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public static void Fmul_V(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2)
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if (AOptimizations.UseSse && AOptimizations.UseSse2)
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{
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EmitSse2CallF(Context, nameof(Sse2.Multiply));
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EmitSseOrSse2CallF(Context, nameof(Sse.Multiply));
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}
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else
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{
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@ -1019,9 +1019,9 @@ namespace ChocolArm64.Instruction
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public static void Fsub_S(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2)
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if (AOptimizations.UseSse && AOptimizations.UseSse2)
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{
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EmitSse2CallF(Context, nameof(Sse2.SubtractScalar));
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EmitSseOrSse2CallF(Context, nameof(Sse.SubtractScalar));
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}
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else
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{
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@ -1031,9 +1031,9 @@ namespace ChocolArm64.Instruction
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public static void Fsub_V(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2)
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if (AOptimizations.UseSse && AOptimizations.UseSse2)
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{
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EmitSse2CallF(Context, nameof(Sse2.Subtract));
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EmitSseOrSse2CallF(Context, nameof(Sse.Subtract));
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}
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else
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{
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@ -19,9 +19,20 @@ namespace ChocolArm64.Instruction
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public static void Cmeq_V(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg Op && Op.Size < 3)
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if (Context.CurrOp is AOpCodeSimdReg Op)
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{
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EmitSse2Call(Context, nameof(Sse2.CompareEqual));
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if (Op.Size < 3 && AOptimizations.UseSse2)
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{
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EmitSse2Call(Context, nameof(Sse2.CompareEqual));
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}
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else if (Op.Size == 3 && AOptimizations.UseSse41)
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{
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EmitSse41Call(Context, nameof(Sse41.CompareEqual));
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}
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else
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{
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EmitCmp(Context, OpCodes.Beq_S, Scalar: false);
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}
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}
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else
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{
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@ -46,9 +57,20 @@ namespace ChocolArm64.Instruction
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public static void Cmgt_V(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg Op && Op.Size < 3)
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if (Context.CurrOp is AOpCodeSimdReg Op)
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{
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EmitSse2Call(Context, nameof(Sse2.CompareGreaterThan));
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if (Op.Size < 3 && AOptimizations.UseSse2)
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{
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EmitSse2Call(Context, nameof(Sse2.CompareGreaterThan));
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}
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else if (Op.Size == 3 && AOptimizations.UseSse42)
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{
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EmitSse42Call(Context, nameof(Sse42.CompareGreaterThan));
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}
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else
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{
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EmitCmp(Context, OpCodes.Bgt_S, Scalar: false);
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}
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}
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else
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{
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@ -133,9 +155,10 @@ namespace ChocolArm64.Instruction
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public static void Fcmeq_S(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg)
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if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse
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&& AOptimizations.UseSse2)
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{
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EmitSse2CallF(Context, nameof(Sse2.CompareEqualScalar));
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EmitSseOrSse2CallF(Context, nameof(Sse.CompareEqualScalar));
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}
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else
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{
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@ -145,9 +168,10 @@ namespace ChocolArm64.Instruction
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public static void Fcmeq_V(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg)
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if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse
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&& AOptimizations.UseSse2)
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{
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EmitSse2CallF(Context, nameof(Sse2.CompareEqual));
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EmitSseOrSse2CallF(Context, nameof(Sse.CompareEqual));
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}
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else
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{
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@ -157,9 +181,10 @@ namespace ChocolArm64.Instruction
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public static void Fcmge_S(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg)
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if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse
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&& AOptimizations.UseSse2)
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{
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EmitSse2CallF(Context, nameof(Sse2.CompareGreaterThanOrEqualScalar));
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EmitSseOrSse2CallF(Context, nameof(Sse.CompareGreaterThanOrEqualScalar));
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}
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else
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{
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@ -169,9 +194,10 @@ namespace ChocolArm64.Instruction
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public static void Fcmge_V(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg)
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if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse
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&& AOptimizations.UseSse2)
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{
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EmitSse2CallF(Context, nameof(Sse2.CompareGreaterThanOrEqual));
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EmitSseOrSse2CallF(Context, nameof(Sse.CompareGreaterThanOrEqual));
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}
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else
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{
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@ -181,9 +207,10 @@ namespace ChocolArm64.Instruction
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public static void Fcmgt_S(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg)
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if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse
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&& AOptimizations.UseSse2)
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{
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EmitSse2CallF(Context, nameof(Sse2.CompareGreaterThanScalar));
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EmitSseOrSse2CallF(Context, nameof(Sse.CompareGreaterThanScalar));
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}
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else
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{
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@ -193,9 +220,10 @@ namespace ChocolArm64.Instruction
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public static void Fcmgt_V(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg)
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if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse
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&& AOptimizations.UseSse2)
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{
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EmitSse2CallF(Context, nameof(Sse2.CompareGreaterThan));
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EmitSseOrSse2CallF(Context, nameof(Sse.CompareGreaterThan));
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}
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else
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{
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@ -3,6 +3,7 @@ using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection;
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using System.Runtime.CompilerServices;
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using System.Runtime.Intrinsics;
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using System.Runtime.Intrinsics.X86;
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@ -34,11 +35,27 @@ namespace ChocolArm64.Instruction
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return (8 << (Op.Size + 1)) - Op.Imm;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static void EmitSse2Call(AILEmitterCtx Context, string Name)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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EmitSseCall(Context, Name, typeof(Sse2));
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}
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int SizeF = Op.Size & 1;
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static void EmitSse41Call(AILEmitterCtx Context, string Name)
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{
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EmitSseCall(Context, Name, typeof(Sse41));
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static void EmitSse42Call(AILEmitterCtx Context, string Name)
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{
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EmitSseCall(Context, Name, typeof(Sse42));
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}
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private static void EmitSseCall(AILEmitterCtx Context, string Name, Type Type)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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void Ldvec(int Reg)
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{
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@ -57,8 +74,6 @@ namespace ChocolArm64.Instruction
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Type BaseType = null;
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Type[] Types;
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switch (Op.Size)
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{
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case 0: BaseType = typeof(Vector128<sbyte>); break;
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@ -71,15 +86,13 @@ namespace ChocolArm64.Instruction
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{
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Ldvec(BinOp.Rm);
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Types = new Type[] { BaseType, BaseType };
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Context.EmitCall(Type.GetMethod(Name, new Type[] { BaseType, BaseType }));
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}
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else
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{
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Types = new Type[] { BaseType };
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Context.EmitCall(Type.GetMethod(Name, new Type[] { BaseType }));
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}
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Context.EmitCall(typeof(Sse2).GetMethod(Name, Types));
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switch (Op.Size)
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{
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case 0: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSByteToSingle)); break;
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@ -96,7 +109,7 @@ namespace ChocolArm64.Instruction
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}
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||||
}
|
||||
|
||||
public static void EmitSse2CallF(AILEmitterCtx Context, string Name)
|
||||
public static void EmitSseOrSse2CallF(AILEmitterCtx Context, string Name)
|
||||
{
|
||||
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
||||
|
||||
@ -114,36 +127,31 @@ namespace ChocolArm64.Instruction
|
||||
|
||||
Ldvec(Op.Rn);
|
||||
|
||||
Type BaseType = SizeF == 0
|
||||
? typeof(Vector128<float>)
|
||||
: typeof(Vector128<double>);
|
||||
Type Type;
|
||||
Type BaseType;
|
||||
|
||||
Type[] Types;
|
||||
if (SizeF == 0)
|
||||
{
|
||||
Type = typeof(Sse);
|
||||
BaseType = typeof(Vector128<float>);
|
||||
}
|
||||
else /* if (SizeF == 1) */
|
||||
{
|
||||
Type = typeof(Sse2);
|
||||
BaseType = typeof(Vector128<double>);
|
||||
}
|
||||
|
||||
if (Op is AOpCodeSimdReg BinOp)
|
||||
{
|
||||
Ldvec(BinOp.Rm);
|
||||
|
||||
Types = new Type[] { BaseType, BaseType };
|
||||
Context.EmitCall(Type.GetMethod(Name, new Type[] { BaseType, BaseType }));
|
||||
}
|
||||
else
|
||||
{
|
||||
Types = new Type[] { BaseType };
|
||||
Context.EmitCall(Type.GetMethod(Name, new Type[] { BaseType }));
|
||||
}
|
||||
|
||||
MethodInfo MthdInfo;
|
||||
|
||||
if (SizeF == 0)
|
||||
{
|
||||
MthdInfo = typeof(Sse).GetMethod(Name, Types);
|
||||
}
|
||||
else /* if (SizeF == 1) */
|
||||
{
|
||||
MthdInfo = typeof(Sse2).GetMethod(Name, Types);
|
||||
}
|
||||
|
||||
Context.EmitCall(MthdInfo);
|
||||
|
||||
if (SizeF == 1)
|
||||
{
|
||||
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorDoubleToSingle));
|
||||
|
@ -113,6 +113,22 @@ namespace Ryujinx.Tests.Cpu
|
||||
return GetThreadState();
|
||||
}
|
||||
|
||||
protected static Vector128<float> MakeVectorE0(double A0)
|
||||
{
|
||||
return Sse.StaticCast<long, float>(Sse2.SetVector128(0, BitConverter.DoubleToInt64Bits(A0)));
|
||||
}
|
||||
|
||||
protected static Vector128<float> MakeVectorE0E1(double A0, double A1)
|
||||
{
|
||||
return Sse.StaticCast<long, float>(Sse2.SetVector128(BitConverter.DoubleToInt64Bits(A1),
|
||||
BitConverter.DoubleToInt64Bits(A0)));
|
||||
}
|
||||
|
||||
protected static Vector128<float> MakeVectorE1(double A1)
|
||||
{
|
||||
return Sse.StaticCast<long, float>(Sse2.SetVector128(BitConverter.DoubleToInt64Bits(A1), 0));
|
||||
}
|
||||
|
||||
protected static double VectorExtractDouble(Vector128<float> Vector, byte Index)
|
||||
{
|
||||
long Value = Sse41.Extract(Sse.StaticCast<float, long>(Vector), Index);
|
||||
@ -120,24 +136,19 @@ namespace Ryujinx.Tests.Cpu
|
||||
return BitConverter.Int64BitsToDouble(Value);
|
||||
}
|
||||
|
||||
protected static Vector128<float> MakeVectorE0(double A)
|
||||
protected static Vector128<float> MakeVectorE0(ulong A0)
|
||||
{
|
||||
return Sse.StaticCast<long, float>(Sse2.SetVector128(0, BitConverter.DoubleToInt64Bits(A)));
|
||||
return Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, A0));
|
||||
}
|
||||
|
||||
protected static Vector128<float> MakeVectorE0(ulong A)
|
||||
protected static Vector128<float> MakeVectorE0E1(ulong A0, ulong A1)
|
||||
{
|
||||
return Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, A));
|
||||
return Sse.StaticCast<ulong, float>(Sse2.SetVector128(A1, A0));
|
||||
}
|
||||
|
||||
protected static Vector128<float> MakeVectorE0E1(ulong A, ulong B)
|
||||
protected static Vector128<float> MakeVectorE1(ulong A1)
|
||||
{
|
||||
return Sse.StaticCast<ulong, float>(Sse2.SetVector128(B, A));
|
||||
}
|
||||
|
||||
protected static Vector128<float> MakeVectorE1(ulong B)
|
||||
{
|
||||
return Sse.StaticCast<ulong, float>(Sse2.SetVector128(B, 0));
|
||||
return Sse.StaticCast<ulong, float>(Sse2.SetVector128(A1, 0));
|
||||
}
|
||||
|
||||
protected static ulong GetVectorE0(Vector128<float> Vector)
|
||||
|
@ -628,6 +628,47 @@ namespace Ryujinx.Tests.Cpu
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("CNT <Vd>.<T>, <Vn>.<T>")]
|
||||
public void Cnt_V_8B([ValueSource("_8B_")] [Random(1)] ulong A)
|
||||
{
|
||||
uint Opcode = 0x0E205820; // CNT V0.8B, V1.8B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
SimdFp.Cnt_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("CNT <Vd>.<T>, <Vn>.<T>")]
|
||||
public void Cnt_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong A1)
|
||||
{
|
||||
uint Opcode = 0x4E205820; // CNT V0.16B, V1.16B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
AArch64.Vpart(1, 1, new Bits(A1));
|
||||
SimdFp.Cnt_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("NEG <V><d>, <V><n>")]
|
||||
public void Neg_S_D([ValueSource("_1D_")] [Random(1)] ulong A)
|
||||
{
|
||||
|
@ -176,10 +176,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
AThreadState ThreadState = SingleOpcode(0x4EA1D802, V0: Sse.SetAllVector128(A));
|
||||
|
||||
Assert.That(Sse41.Extract(ThreadState.V2, (byte)0), Is.EqualTo(1 / A));
|
||||
Assert.That(Sse41.Extract(ThreadState.V2, (byte)1), Is.EqualTo(1 / A));
|
||||
Assert.That(Sse41.Extract(ThreadState.V2, (byte)2), Is.EqualTo(1 / A));
|
||||
Assert.That(Sse41.Extract(ThreadState.V2, (byte)3), Is.EqualTo(1 / A));
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(Sse41.Extract(ThreadState.V2, (byte)0), Is.EqualTo(1 / A));
|
||||
Assert.That(Sse41.Extract(ThreadState.V2, (byte)1), Is.EqualTo(1 / A));
|
||||
Assert.That(Sse41.Extract(ThreadState.V2, (byte)2), Is.EqualTo(1 / A));
|
||||
Assert.That(Sse41.Extract(ThreadState.V2, (byte)3), Is.EqualTo(1 / A));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("FRECPS D0, D1, D2")]
|
||||
@ -199,10 +202,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
V2: Sse.SetAllVector128(A),
|
||||
V0: Sse.SetAllVector128(B));
|
||||
|
||||
Assert.That(Sse41.Extract(ThreadState.V4, (byte)0), Is.EqualTo(2 - (A * B)));
|
||||
Assert.That(Sse41.Extract(ThreadState.V4, (byte)1), Is.EqualTo(2 - (A * B)));
|
||||
Assert.That(Sse41.Extract(ThreadState.V4, (byte)2), Is.EqualTo(2 - (A * B)));
|
||||
Assert.That(Sse41.Extract(ThreadState.V4, (byte)3), Is.EqualTo(2 - (A * B)));
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(Sse41.Extract(ThreadState.V4, (byte)0), Is.EqualTo(2 - (A * B)));
|
||||
Assert.That(Sse41.Extract(ThreadState.V4, (byte)1), Is.EqualTo(2 - (A * B)));
|
||||
Assert.That(Sse41.Extract(ThreadState.V4, (byte)2), Is.EqualTo(2 - (A * B)));
|
||||
Assert.That(Sse41.Extract(ThreadState.V4, (byte)3), Is.EqualTo(2 - (A * B)));
|
||||
});
|
||||
}
|
||||
|
||||
[TestCase(0x3FE66666u, false, 0x40000000u)]
|
||||
|
375
Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs
Normal file
375
Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs
Normal file
@ -0,0 +1,375 @@
|
||||
using ChocolArm64.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System;
|
||||
using System.Runtime.Intrinsics;
|
||||
using System.Runtime.Intrinsics.X86;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
public class CpuTestSimdCmp : CpuTest
|
||||
{
|
||||
#region "ValueSource"
|
||||
private static float[] _floats_()
|
||||
{
|
||||
return new float[] { float.NegativeInfinity, float.MinValue, -1f, -0f,
|
||||
+0f, +1f, float.MaxValue, float.PositiveInfinity };
|
||||
}
|
||||
|
||||
private static double[] _doubles_()
|
||||
{
|
||||
return new double[] { double.NegativeInfinity, double.MinValue, -1d, -0d,
|
||||
+0d, +1d, double.MaxValue, double.PositiveInfinity };
|
||||
}
|
||||
#endregion
|
||||
|
||||
[Test, Description("FCMEQ D0, D1, D2 | FCMGE D0, D1, D2 | FCMGT D0, D1, D2")]
|
||||
public void Fcmeq_Fcmge_Fcmgt_Reg_S_D([ValueSource("_doubles_")] [Random(8)] double A,
|
||||
[ValueSource("_doubles_")] [Random(8)] double B,
|
||||
[Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT
|
||||
{
|
||||
uint Opcode = 0x5E62E420 | ((EU & 1) << 29) | ((EU >> 1) << 23);
|
||||
Vector128<float> V0 = Sse.StaticCast<double, float>(Sse2.SetAllVector128(TestContext.CurrentContext.Random.NextDouble()));
|
||||
Vector128<float> V1 = Sse.StaticCast<double, float>(Sse2.SetScalarVector128(A));
|
||||
Vector128<float> V2 = Sse.StaticCast<double, float>(Sse2.SetScalarVector128(B));
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
byte[] Exp = default(byte[]);
|
||||
byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
|
||||
byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
|
||||
|
||||
switch (EU)
|
||||
{
|
||||
case 0: Exp = (A == B ? Ones : Zeros); break;
|
||||
case 1: Exp = (A >= B ? Ones : Zeros); break;
|
||||
case 3: Exp = (A > B ? Ones : Zeros); break;
|
||||
}
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp));
|
||||
Assert.That(VectorExtractDouble(ThreadState.V0, (byte)1), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("FCMEQ S0, S1, S2 | FCMGE S0, S1, S2 | FCMGT S0, S1, S2")]
|
||||
public void Fcmeq_Fcmge_Fcmgt_Reg_S_S([ValueSource("_floats_")] [Random(8)] float A,
|
||||
[ValueSource("_floats_")] [Random(8)] float B,
|
||||
[Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT
|
||||
{
|
||||
uint Opcode = 0x5E22E420 | ((EU & 1) << 29) | ((EU >> 1) << 23);
|
||||
Vector128<float> V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat());
|
||||
Vector128<float> V1 = Sse.SetScalarVector128(A);
|
||||
Vector128<float> V2 = Sse.SetScalarVector128(B);
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
byte[] Exp = default(byte[]);
|
||||
byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF};
|
||||
byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00};
|
||||
|
||||
switch (EU)
|
||||
{
|
||||
case 0: Exp = (A == B ? Ones : Zeros); break;
|
||||
case 1: Exp = (A >= B ? Ones : Zeros); break;
|
||||
case 3: Exp = (A > B ? Ones : Zeros); break;
|
||||
}
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp));
|
||||
Assert.That(Sse41.Extract(ThreadState.V0, (byte)1), Is.Zero);
|
||||
Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero);
|
||||
Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("FCMEQ V0.2D, V1.2D, V2.2D | FCMGE V0.2D, V1.2D, V2.2D | FCMGT V0.2D, V1.2D, V2.2D")]
|
||||
public void Fcmeq_Fcmge_Fcmgt_Reg_V_2D([ValueSource("_doubles_")] [Random(8)] double A,
|
||||
[ValueSource("_doubles_")] [Random(8)] double B,
|
||||
[Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT
|
||||
{
|
||||
uint Opcode = 0x4E62E420 | ((EU & 1) << 29) | ((EU >> 1) << 23);
|
||||
Vector128<float> V1 = Sse.StaticCast<double, float>(Sse2.SetAllVector128(A));
|
||||
Vector128<float> V2 = Sse.StaticCast<double, float>(Sse2.SetAllVector128(B));
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
byte[] Exp = default(byte[]);
|
||||
byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
|
||||
byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
|
||||
|
||||
switch (EU)
|
||||
{
|
||||
case 0: Exp = (A == B ? Ones : Zeros); break;
|
||||
case 1: Exp = (A >= B ? Ones : Zeros); break;
|
||||
case 3: Exp = (A > B ? Ones : Zeros); break;
|
||||
}
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp));
|
||||
Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("FCMEQ V0.2S, V1.2S, V2.2S | FCMGE V0.2S, V1.2S, V2.2S | FCMGT V0.2S, V1.2S, V2.2S")]
|
||||
public void Fcmeq_Fcmge_Fcmgt_Reg_V_2S([ValueSource("_floats_")] [Random(8)] float A,
|
||||
[ValueSource("_floats_")] [Random(8)] float B,
|
||||
[Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT
|
||||
{
|
||||
uint Opcode = 0x0E22E420 | ((EU & 1) << 29) | ((EU >> 1) << 23);
|
||||
Vector128<float> V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat());
|
||||
Vector128<float> V1 = Sse.SetVector128(0, 0, A, A);
|
||||
Vector128<float> V2 = Sse.SetVector128(0, 0, B, B);
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
byte[] Exp = default(byte[]);
|
||||
byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF};
|
||||
byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00};
|
||||
|
||||
switch (EU)
|
||||
{
|
||||
case 0: Exp = (A == B ? Ones : Zeros); break;
|
||||
case 1: Exp = (A >= B ? Ones : Zeros); break;
|
||||
case 3: Exp = (A > B ? Ones : Zeros); break;
|
||||
}
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp));
|
||||
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp));
|
||||
Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero);
|
||||
Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("FCMEQ V0.4S, V1.4S, V2.4S | FCMGE V0.4S, V1.4S, V2.4S | FCMGT V0.4S, V1.4S, V2.4S")]
|
||||
public void Fcmeq_Fcmge_Fcmgt_Reg_V_4S([ValueSource("_floats_")] [Random(8)] float A,
|
||||
[ValueSource("_floats_")] [Random(8)] float B,
|
||||
[Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT
|
||||
{
|
||||
uint Opcode = 0x4E22E420 | ((EU & 1) << 29) | ((EU >> 1) << 23);
|
||||
Vector128<float> V1 = Sse.SetAllVector128(A);
|
||||
Vector128<float> V2 = Sse.SetAllVector128(B);
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
byte[] Exp = default(byte[]);
|
||||
byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF};
|
||||
byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00};
|
||||
|
||||
switch (EU)
|
||||
{
|
||||
case 0: Exp = (A == B ? Ones : Zeros); break;
|
||||
case 1: Exp = (A >= B ? Ones : Zeros); break;
|
||||
case 3: Exp = (A > B ? Ones : Zeros); break;
|
||||
}
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp));
|
||||
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp));
|
||||
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)2)), Is.EquivalentTo(Exp));
|
||||
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)3)), Is.EquivalentTo(Exp));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("FCMGT D0, D1, #0.0 | FCMGE D0, D1, #0.0 | FCMEQ D0, D1, #0.0 | FCMLE D0, D1, #0.0 | FCMLT D0, D1, #0.0")]
|
||||
public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_D([ValueSource("_doubles_")] [Random(8)] double A,
|
||||
[Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE
|
||||
[Values(0u, 1u)] uint bit13) // "LT"
|
||||
{
|
||||
uint Opcode = 0x5EE0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12);
|
||||
Vector128<float> V0 = Sse.StaticCast<double, float>(Sse2.SetAllVector128(TestContext.CurrentContext.Random.NextDouble()));
|
||||
Vector128<float> V1 = Sse.StaticCast<double, float>(Sse2.SetScalarVector128(A));
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
double Zero = +0d;
|
||||
byte[] Exp = default(byte[]);
|
||||
byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
|
||||
byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
|
||||
|
||||
if (bit13 == 0)
|
||||
{
|
||||
switch (opU)
|
||||
{
|
||||
case 0: Exp = (A > Zero ? Ones : Zeros); break;
|
||||
case 1: Exp = (A >= Zero ? Ones : Zeros); break;
|
||||
case 2: Exp = (A == Zero ? Ones : Zeros); break;
|
||||
case 3: Exp = (Zero >= A ? Ones : Zeros); break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
Exp = (Zero > A ? Ones : Zeros);
|
||||
}
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp));
|
||||
Assert.That(VectorExtractDouble(ThreadState.V0, (byte)1), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("FCMGT S0, S1, #0.0 | FCMGE S0, S1, #0.0 | FCMEQ S0, S1, #0.0 | FCMLE S0, S1, #0.0 | FCMLT S0, S1, #0.0")]
|
||||
public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_S([ValueSource("_floats_")] [Random(8)] float A,
|
||||
[Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE
|
||||
[Values(0u, 1u)] uint bit13) // "LT"
|
||||
{
|
||||
uint Opcode = 0x5EA0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12);
|
||||
Vector128<float> V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat());
|
||||
Vector128<float> V1 = Sse.SetScalarVector128(A);
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
float Zero = +0f;
|
||||
byte[] Exp = default(byte[]);
|
||||
byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF};
|
||||
byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00};
|
||||
|
||||
if (bit13 == 0)
|
||||
{
|
||||
switch (opU)
|
||||
{
|
||||
case 0: Exp = (A > Zero ? Ones : Zeros); break;
|
||||
case 1: Exp = (A >= Zero ? Ones : Zeros); break;
|
||||
case 2: Exp = (A == Zero ? Ones : Zeros); break;
|
||||
case 3: Exp = (Zero >= A ? Ones : Zeros); break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
Exp = (Zero > A ? Ones : Zeros);
|
||||
}
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp));
|
||||
Assert.That(Sse41.Extract(ThreadState.V0, (byte)1), Is.Zero);
|
||||
Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero);
|
||||
Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("FCMGT V0.2D, V1.2D, #0.0 | FCMGE V0.2D, V1.2D, #0.0 | FCMEQ V0.2D, V1.2D, #0.0 | FCMLE V0.2D, V1.2D, #0.0 | FCMLT V0.2D, V1.2D, #0.0")]
|
||||
public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2D([ValueSource("_doubles_")] [Random(8)] double A,
|
||||
[Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE
|
||||
[Values(0u, 1u)] uint bit13) // "LT"
|
||||
{
|
||||
uint Opcode = 0x4EE0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12);
|
||||
Vector128<float> V1 = Sse.StaticCast<double, float>(Sse2.SetAllVector128(A));
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
|
||||
|
||||
double Zero = +0d;
|
||||
byte[] Exp = default(byte[]);
|
||||
byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
|
||||
byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
|
||||
|
||||
if (bit13 == 0)
|
||||
{
|
||||
switch (opU)
|
||||
{
|
||||
case 0: Exp = (A > Zero ? Ones : Zeros); break;
|
||||
case 1: Exp = (A >= Zero ? Ones : Zeros); break;
|
||||
case 2: Exp = (A == Zero ? Ones : Zeros); break;
|
||||
case 3: Exp = (Zero >= A ? Ones : Zeros); break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
Exp = (Zero > A ? Ones : Zeros);
|
||||
}
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp));
|
||||
Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("FCMGT V0.2S, V1.2S, #0.0 | FCMGE V0.2S, V1.2S, #0.0 | FCMEQ V0.2S, V1.2S, #0.0 | FCMLE V0.2S, V1.2S, #0.0 | FCMLT V0.2S, V1.2S, #0.0")]
|
||||
public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2S([ValueSource("_floats_")] [Random(8)] float A,
|
||||
[Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE
|
||||
[Values(0u, 1u)] uint bit13) // "LT"
|
||||
{
|
||||
uint Opcode = 0x0EA0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12);
|
||||
Vector128<float> V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat());
|
||||
Vector128<float> V1 = Sse.SetVector128(0, 0, A, A);
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
float Zero = +0f;
|
||||
byte[] Exp = default(byte[]);
|
||||
byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF};
|
||||
byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00};
|
||||
|
||||
if (bit13 == 0)
|
||||
{
|
||||
switch (opU)
|
||||
{
|
||||
case 0: Exp = (A > Zero ? Ones : Zeros); break;
|
||||
case 1: Exp = (A >= Zero ? Ones : Zeros); break;
|
||||
case 2: Exp = (A == Zero ? Ones : Zeros); break;
|
||||
case 3: Exp = (Zero >= A ? Ones : Zeros); break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
Exp = (Zero > A ? Ones : Zeros);
|
||||
}
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp));
|
||||
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp));
|
||||
Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero);
|
||||
Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("FCMGT V0.4S, V1.4S, #0.0 | FCMGE V0.4S, V1.4S, #0.0 | FCMEQ V0.4S, V1.4S, #0.0 | FCMLE V0.4S, V1.4S, #0.0 | FCMLT V0.4S, V1.4S, #0.0")]
|
||||
public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_4S([ValueSource("_floats_")] [Random(8)] float A,
|
||||
[Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE
|
||||
[Values(0u, 1u)] uint bit13) // "LT"
|
||||
{
|
||||
uint Opcode = 0x4EA0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12);
|
||||
Vector128<float> V1 = Sse.SetAllVector128(A);
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
|
||||
|
||||
float Zero = +0f;
|
||||
byte[] Exp = default(byte[]);
|
||||
byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF};
|
||||
byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00};
|
||||
|
||||
if (bit13 == 0)
|
||||
{
|
||||
switch (opU)
|
||||
{
|
||||
case 0: Exp = (A > Zero ? Ones : Zeros); break;
|
||||
case 1: Exp = (A >= Zero ? Ones : Zeros); break;
|
||||
case 2: Exp = (A == Zero ? Ones : Zeros); break;
|
||||
case 3: Exp = (Zero >= A ? Ones : Zeros); break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
Exp = (Zero > A ? Ones : Zeros);
|
||||
}
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp));
|
||||
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp));
|
||||
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)2)), Is.EquivalentTo(Exp));
|
||||
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)3)), Is.EquivalentTo(Exp));
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
@ -19,12 +19,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)0);
|
||||
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)0), Is.EqualTo(A0));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)1), Is.EqualTo(B0));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)2), Is.EqualTo(A2));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)3), Is.EqualTo(B2));
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)0), Is.EqualTo(A0));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)1), Is.EqualTo(B0));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)2), Is.EqualTo(A2));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)3), Is.EqualTo(B2));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("TRN1 V0.8B, V1.8B, V2.8B")]
|
||||
@ -39,14 +40,17 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)0), Is.EqualTo(A0));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)1), Is.EqualTo(B0));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)2), Is.EqualTo(A2));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)3), Is.EqualTo(B2));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)4), Is.EqualTo(A4));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)5), Is.EqualTo(B4));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)6), Is.EqualTo(A6));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)7), Is.EqualTo(B6));
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)0), Is.EqualTo(A0));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)1), Is.EqualTo(B0));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)2), Is.EqualTo(A2));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)3), Is.EqualTo(B2));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)4), Is.EqualTo(A4));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)5), Is.EqualTo(B4));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)6), Is.EqualTo(A6));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)7), Is.EqualTo(B6));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("TRN2 V0.4S, V1.4S, V2.4S")]
|
||||
@ -59,10 +63,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)0), Is.EqualTo(A1));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)1), Is.EqualTo(B1));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)2), Is.EqualTo(A3));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)3), Is.EqualTo(B3));
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)0), Is.EqualTo(A1));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)1), Is.EqualTo(B1));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)2), Is.EqualTo(A3));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)3), Is.EqualTo(B3));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("TRN2 V0.8B, V1.8B, V2.8B")]
|
||||
@ -77,14 +84,17 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)0), Is.EqualTo(A1));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)1), Is.EqualTo(B1));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)2), Is.EqualTo(A3));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)3), Is.EqualTo(B3));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)4), Is.EqualTo(A5));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)5), Is.EqualTo(B5));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)6), Is.EqualTo(A7));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)7), Is.EqualTo(B7));
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)0), Is.EqualTo(A1));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)1), Is.EqualTo(B1));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)2), Is.EqualTo(A3));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)3), Is.EqualTo(B3));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)4), Is.EqualTo(A5));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)5), Is.EqualTo(B5));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)6), Is.EqualTo(A7));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)7), Is.EqualTo(B7));
|
||||
});
|
||||
}
|
||||
|
||||
[TestCase(0u, 0u, 0x2313221221112010ul, 0x0000000000000000ul)]
|
||||
|
@ -1826,7 +1826,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
||||
// addp_advsimd_pair.html
|
||||
public static void Addp_S(Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode Scalar */
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
@ -1875,7 +1875,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
||||
{
|
||||
const bool U = false;
|
||||
|
||||
/* Decode */
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
@ -1917,7 +1917,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
||||
{
|
||||
const bool U = true;
|
||||
|
||||
/* Decode */
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
@ -2654,6 +2654,37 @@ namespace Ryujinx.Tests.Cpu.Tester
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// cnt_advsimd.html
|
||||
public static void Cnt_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
/* if size != '00' then ReservedValue(); */
|
||||
|
||||
int esize = 8;
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / 8;
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
|
||||
BigInteger count;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
count = (BigInteger)BitCount(Elem(operand, e, esize));
|
||||
|
||||
Elem(result, e, esize, count.SubBigInteger(esize - 1, 0));
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// neg_advsimd.html#NEG_asisdmisc_R
|
||||
public static void Neg_S(Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
@ -2745,7 +2776,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
||||
// not_advsimd.html
|
||||
public static void Not_V(bool Q, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode */
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
@ -3095,7 +3126,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
||||
// addp_advsimd_vec.html
|
||||
public static void Addp_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode Vector */
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
@ -586,6 +586,24 @@ namespace Ryujinx.Tests.Cpu.Tester
|
||||
return (x >= 0 ? x : -x);
|
||||
}
|
||||
|
||||
// shared_pseudocode.html#impl-shared.BitCount.1
|
||||
public static int BitCount(Bits x)
|
||||
{
|
||||
int N = x.Count;
|
||||
|
||||
int result = 0;
|
||||
|
||||
for (int i = 0; i <= N - 1; i++)
|
||||
{
|
||||
if (x[i])
|
||||
{
|
||||
result = result + 1;
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
// shared_pseudocode.html#impl-shared.CountLeadingSignBits.1
|
||||
public static int CountLeadingSignBits(Bits x)
|
||||
{
|
||||
|
Loading…
Reference in New Issue
Block a user