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Add UHADD instruction
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@ -184,7 +184,7 @@ namespace ChocolArm64
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Set("x00111100x111001000000xxxxxxxxxx", AInstEmit.Fcvtzu_Gp, typeof(AOpCodeSimdCvt));
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Set("x00111100x011001xxxxxxxxxxxxxxxx", AInstEmit.Fcvtzu_Gp_Fix, typeof(AOpCodeSimdCvt));
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Set("0>1011101<100001101110xxxxxxxxxx", AInstEmit.Fcvtzu_V, typeof(AOpCodeSimd));
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Set("0x1011110>>xxxxx111111xxxxxxxxxx", AInstEmit.Fcvtzu_V, typeof(AOpCodeSimdShImm));
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Set("0x1011110>>xxxxx111111xxxxxxxxxx", AInstEmit.Fcvtzu_V, typeof(AOpCodeSimdShImm));
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Set("000111100x1xxxxx000110xxxxxxxxxx", AInstEmit.Fdiv_S, typeof(AOpCodeSimdReg));
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Set("0>1011100<1xxxxx111111xxxxxxxxxx", AInstEmit.Fdiv_V, typeof(AOpCodeSimdReg));
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Set("000111110x0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Fmadd_S, typeof(AOpCodeSimdReg));
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@ -220,7 +220,7 @@ namespace ChocolArm64
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Set("000111100x100100110000xxxxxxxxxx", AInstEmit.Frintp_S, typeof(AOpCodeSimd));
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Set("0>0011101<100001100010xxxxxxxxxx", AInstEmit.Frintp_V, typeof(AOpCodeSimd));
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Set("000111100x100111010000xxxxxxxxxx", AInstEmit.Frintx_S, typeof(AOpCodeSimd));
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Set("0>1011100<100001100110xxxxxxxxxx", AInstEmit.Frintx_V, typeof(AOpCodeSimd));
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Set("0>1011100<100001100110xxxxxxxxxx", AInstEmit.Frintx_V, typeof(AOpCodeSimd));
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Set("000111100x100001110000xxxxxxxxxx", AInstEmit.Fsqrt_S, typeof(AOpCodeSimd));
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Set("000111100x1xxxxx001110xxxxxxxxxx", AInstEmit.Fsub_S, typeof(AOpCodeSimdReg));
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Set("0>0011101<1xxxxx110101xxxxxxxxxx", AInstEmit.Fsub_V, typeof(AOpCodeSimdReg));
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@ -291,6 +291,7 @@ namespace ChocolArm64
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Set("x0011110xx100011000000xxxxxxxxxx", AInstEmit.Ucvtf_Gp, typeof(AOpCodeSimdCvt));
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Set("011111100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_S, typeof(AOpCodeSimd));
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Set("0x1011100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_V, typeof(AOpCodeSimd));
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Set("0x101110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Uhadd_V, typeof(AOpCodeSimdReg));
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Set("0x001110000xxxxx001111xxxxxxxxxx", AInstEmit.Umov_S, typeof(AOpCodeSimdIns));
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Set("0x101110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Umull_V, typeof(AOpCodeSimdReg));
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Set("0>101110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Ushl_V, typeof(AOpCodeSimdReg));
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@ -247,7 +247,7 @@ namespace ChocolArm64.Instruction
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int SizeF = Op.Size & 1;
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EmitVectorExtractF(Context, Op.Rn, 0, SizeF);
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EmitVectorExtractF(Context, Op.Rm, 0, SizeF);
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@ -316,7 +316,7 @@ namespace ChocolArm64.Instruction
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public static void Frinti_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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EmitVectorUnaryOpF(Context, () =>
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{
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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@ -324,11 +324,11 @@ namespace ChocolArm64.Instruction
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Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpcr));
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if (Op.Size == 2)
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{
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.RoundF));
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}
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else if (Op.Size == 3)
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{
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Round));
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}
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else
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@ -425,11 +425,11 @@ namespace ChocolArm64.Instruction
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Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpcr));
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if (Op.Size == 0)
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{
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.RoundF));
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}
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else if (Op.Size == 1)
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{
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Round));
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}
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else
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@ -569,6 +569,18 @@ namespace ChocolArm64.Instruction
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EmitVectorWidenRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
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}
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public static void Uhadd_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryOpZx(Context, () =>
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{
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Context.Emit(OpCodes.Add);
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Context.EmitLdc_I4(1);
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Context.Emit(OpCodes.Shr_Un);
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});
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}
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public static void Umull_V(AILEmitterCtx Context)
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{
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EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
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