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Lower precision of estimate instruction results to match Arm behavior (#1943)
* Lower precision of estimate instruction results to match Arm behavior * PTC version update * Nits
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98d0240ce6
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@ -1475,9 +1475,11 @@ namespace ARMeilleure.Instructions
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int sizeF = op.Size & 1;
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if (Optimizations.FastFP && Optimizations.UseSse && sizeF == 0)
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if (Optimizations.FastFP && Optimizations.UseSse41 && sizeF == 0)
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{
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EmitScalarUnaryOpF(context, Intrinsic.X86Rcpss, 0);
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Operand res = EmitSse41FP32RoundExp8(context, context.AddIntrinsic(Intrinsic.X86Rcpss, GetVec(op.Rn)), scalar: true);
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context.Copy(GetVec(op.Rd), context.VectorZeroUpper96(res));
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}
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else
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{
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@ -1494,9 +1496,16 @@ namespace ARMeilleure.Instructions
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int sizeF = op.Size & 1;
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if (Optimizations.FastFP && Optimizations.UseSse && sizeF == 0)
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if (Optimizations.FastFP && Optimizations.UseSse41 && sizeF == 0)
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{
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EmitVectorUnaryOpF(context, Intrinsic.X86Rcpps, 0);
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Operand res = EmitSse41FP32RoundExp8(context, context.AddIntrinsic(Intrinsic.X86Rcpps, GetVec(op.Rn)), scalar: false);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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@ -1652,7 +1661,7 @@ namespace ARMeilleure.Instructions
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{
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if (Optimizations.UseSse41)
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{
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EmitScalarRoundOpF(context, FPRoundingMode.TowardsMinusInfinity);
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EmitSse41ScalarRoundOpF(context, FPRoundingMode.TowardsMinusInfinity);
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}
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else
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{
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@ -1667,7 +1676,7 @@ namespace ARMeilleure.Instructions
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{
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if (Optimizations.UseSse41)
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{
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EmitVectorRoundOpF(context, FPRoundingMode.TowardsMinusInfinity);
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EmitSse41VectorRoundOpF(context, FPRoundingMode.TowardsMinusInfinity);
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}
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else
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{
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@ -1682,7 +1691,7 @@ namespace ARMeilleure.Instructions
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{
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if (Optimizations.UseSse41)
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{
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EmitScalarRoundOpF(context, FPRoundingMode.ToNearest);
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EmitSse41ScalarRoundOpF(context, FPRoundingMode.ToNearest);
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}
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else
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{
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@ -1697,7 +1706,7 @@ namespace ARMeilleure.Instructions
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{
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if (Optimizations.UseSse41)
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{
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EmitVectorRoundOpF(context, FPRoundingMode.ToNearest);
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EmitSse41VectorRoundOpF(context, FPRoundingMode.ToNearest);
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}
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else
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{
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@ -1712,7 +1721,7 @@ namespace ARMeilleure.Instructions
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{
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if (Optimizations.UseSse41)
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{
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EmitScalarRoundOpF(context, FPRoundingMode.TowardsPlusInfinity);
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EmitSse41ScalarRoundOpF(context, FPRoundingMode.TowardsPlusInfinity);
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}
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else
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{
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@ -1727,7 +1736,7 @@ namespace ARMeilleure.Instructions
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{
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if (Optimizations.UseSse41)
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{
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EmitVectorRoundOpF(context, FPRoundingMode.TowardsPlusInfinity);
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EmitSse41VectorRoundOpF(context, FPRoundingMode.TowardsPlusInfinity);
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}
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else
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{
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@ -1778,7 +1787,7 @@ namespace ARMeilleure.Instructions
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{
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if (Optimizations.UseSse41)
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{
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EmitScalarRoundOpF(context, FPRoundingMode.TowardsZero);
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EmitSse41ScalarRoundOpF(context, FPRoundingMode.TowardsZero);
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}
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else
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{
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@ -1793,7 +1802,7 @@ namespace ARMeilleure.Instructions
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{
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if (Optimizations.UseSse41)
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{
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EmitVectorRoundOpF(context, FPRoundingMode.TowardsZero);
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EmitSse41VectorRoundOpF(context, FPRoundingMode.TowardsZero);
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}
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else
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{
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@ -1810,9 +1819,11 @@ namespace ARMeilleure.Instructions
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int sizeF = op.Size & 1;
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if (Optimizations.FastFP && Optimizations.UseSse && sizeF == 0)
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if (Optimizations.FastFP && Optimizations.UseSse41 && sizeF == 0)
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{
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EmitScalarUnaryOpF(context, Intrinsic.X86Rsqrtss, 0);
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Operand res = EmitSse41FP32RoundExp8(context, context.AddIntrinsic(Intrinsic.X86Rsqrtss, GetVec(op.Rn)), scalar: true);
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context.Copy(GetVec(op.Rd), context.VectorZeroUpper96(res));
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}
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else
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{
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@ -1829,9 +1840,16 @@ namespace ARMeilleure.Instructions
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int sizeF = op.Size & 1;
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if (Optimizations.FastFP && Optimizations.UseSse && sizeF == 0)
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if (Optimizations.FastFP && Optimizations.UseSse41 && sizeF == 0)
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{
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EmitVectorUnaryOpF(context, Intrinsic.X86Rsqrtps, 0);
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Operand res = EmitSse41FP32RoundExp8(context, context.AddIntrinsic(Intrinsic.X86Rsqrtps, GetVec(op.Rn)), scalar: false);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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@ -3498,7 +3516,7 @@ namespace ARMeilleure.Instructions
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return context.ConditionalSelect(cmp, op1, op2);
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}
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private static void EmitScalarRoundOpF(ArmEmitterContext context, FPRoundingMode roundMode)
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private static void EmitSse41ScalarRoundOpF(ArmEmitterContext context, FPRoundingMode roundMode)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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@ -3520,7 +3538,7 @@ namespace ARMeilleure.Instructions
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context.Copy(GetVec(op.Rd), res);
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}
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private static void EmitVectorRoundOpF(ArmEmitterContext context, FPRoundingMode roundMode)
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private static void EmitSse41VectorRoundOpF(ArmEmitterContext context, FPRoundingMode roundMode)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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@ -3538,6 +3556,35 @@ namespace ARMeilleure.Instructions
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context.Copy(GetVec(op.Rd), res);
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}
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private static Operand EmitSse41FP32RoundExp8(ArmEmitterContext context, Operand value, bool scalar)
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{
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Operand roundMask;
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Operand truncMask;
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Operand expMask;
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if (scalar)
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{
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roundMask = X86GetScalar(context, 0x4000);
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truncMask = X86GetScalar(context, unchecked((int)0xFFFF8000));
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expMask = X86GetScalar(context, 0x7F800000);
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}
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else
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{
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roundMask = X86GetAllElements(context, 0x4000);
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truncMask = X86GetAllElements(context, unchecked((int)0xFFFF8000));
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expMask = X86GetAllElements(context, 0x7F800000);
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}
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Operand oValue = value;
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Operand masked = context.AddIntrinsic(Intrinsic.X86Pand, value, expMask);
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Operand isNaNInf = context.AddIntrinsic(Intrinsic.X86Pcmpeqw, masked, expMask);
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value = context.AddIntrinsic(Intrinsic.X86Paddw, value, roundMask);
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value = context.AddIntrinsic(Intrinsic.X86Pand, value, truncMask);
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return context.AddIntrinsic(Intrinsic.X86Blendvps, value, oValue, isNaNInf);
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}
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public static void EmitSse2VectorIsNaNOpF(
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ArmEmitterContext context,
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Operand opF,
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@ -22,7 +22,7 @@ namespace ARMeilleure.Translation.PTC
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{
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private const string HeaderMagic = "PTChd";
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private const int InternalVersion = 1956; //! To be incremented manually for each change to the ARMeilleure project.
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private const int InternalVersion = 1943; //! To be incremented manually for each change to the ARMeilleure project.
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private const string ActualDir = "0";
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private const string BackupDir = "1";
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