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CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776)
* Start implementation * Draft * Updated opcode. Needs verification. * Clean up code. * Update implementation and tests. * Update implemenation + tests * Get RM from FPSCR + Do not use emit/addintrinsic * Remove "fast" path, as recommended by gdk. * Variable DELETED. * Update ARMeilleure/Decoders/OpCodeTable.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Move method * stringing things together :) Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
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@ -912,6 +912,7 @@ namespace ARMeilleure.Decoders
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SetA32("111100111x11xx00xxxx000<<xx0xxxx", InstName.Vrev, InstEmit32.Vrev, OpCode32SimdRev.Create);
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SetA32("111111101x1110xxxxxx101x01x0xxxx", InstName.Vrint, InstEmit32.Vrint_RM, OpCode32SimdS.Create);
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SetA32("<<<<11101x110110xxxx101x11x0xxxx", InstName.Vrint, InstEmit32.Vrint_Z, OpCode32SimdS.Create);
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SetA32("<<<<11101x110111xxxx101x01x0xxxx", InstName.Vrintx, InstEmit32.Vrintx_S, OpCode32SimdS.Create);
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SetA32("1111001x1x>>>xxxxxxx0010>xx1xxxx", InstName.Vrshr, InstEmit32.Vrshr, OpCode32SimdShImm.Create);
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SetA32("111100111x111011xxxx010x1xx0xxxx", InstName.Vrsqrte, InstEmit32.Vrsqrte, OpCode32SimdSqrte.Create);
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SetA32("111100100x10xxxxxxxx1111xxx1xxxx", InstName.Vrsqrts, InstEmit32.Vrsqrts, OpCode32SimdReg.Create);
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@ -342,6 +342,21 @@ namespace ARMeilleure.Instructions
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}
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}
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// VRINTX (floating-point).
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public static void Vrintx_S(ArmEmitterContext context)
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{
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OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
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bool doubleSize = (op.Size & 1) == 1;
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string methodName = doubleSize ? nameof(SoftFallback.Round) : nameof(SoftFallback.RoundF);
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EmitScalarUnaryOpF32(context, (op1) =>
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{
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MethodInfo info = typeof(SoftFallback).GetMethod(methodName);
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return context.Call(info, op1);
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});
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}
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private static Operand EmitFPConvert(ArmEmitterContext context, Operand value, OperandType type, bool signed)
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{
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Debug.Assert(value.Type == OperandType.I32 || value.Type == OperandType.I64);
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@ -608,6 +608,7 @@ namespace ARMeilleure.Instructions
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Vqshrn,
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Vrev,
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Vrint,
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Vrintx,
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Vrshr,
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Vsel,
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Vshl,
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@ -2,6 +2,7 @@
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using ARMeilleure.State;
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using NUnit.Framework;
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using System;
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using System.Collections.Generic;
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namespace Ryujinx.Tests.Cpu
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@ -215,6 +216,42 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VRINTX.F<size> <Sd>, <Sm>")]
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public void Vrintx_S([Values(0u, 1u)] uint rd,
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[Values(0u, 1u)] uint rm,
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[Values(2u, 3u)] uint size,
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[ValueSource(nameof(_1D_F_))] ulong s0,
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[ValueSource(nameof(_1D_F_))] ulong s1,
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[ValueSource(nameof(_1D_F_))] ulong s2,
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[Values(RMode.Rn, RMode.Rm, RMode.Rp)] RMode rMode)
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{
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uint opcode = 0xEB70A40;
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V128 v0, v1, v2;
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if (size == 2)
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{
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opcode |= ((rm & 0x1e) >> 1) | ((rm & 0x1) << 5);
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opcode |= ((rd & 0x1e) >> 11) | ((rm & 0x1) << 22);
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v0 = MakeVectorE0E1((uint)BitConverter.SingleToInt32Bits(s0), (uint)BitConverter.SingleToInt32Bits(s0));
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v1 = MakeVectorE0E1((uint)BitConverter.SingleToInt32Bits(s1), (uint)BitConverter.SingleToInt32Bits(s0));
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v2 = MakeVectorE0E1((uint)BitConverter.SingleToInt32Bits(s2), (uint)BitConverter.SingleToInt32Bits(s1));
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}
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else
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{
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opcode |= ((rm & 0xf) << 0) | ((rd & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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v0 = MakeVectorE0E1((uint)BitConverter.DoubleToInt64Bits(s0), (uint)BitConverter.DoubleToInt64Bits(s0));
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v1 = MakeVectorE0E1((uint)BitConverter.DoubleToInt64Bits(s1), (uint)BitConverter.DoubleToInt64Bits(s0));
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v2 = MakeVectorE0E1((uint)BitConverter.DoubleToInt64Bits(s2), (uint)BitConverter.DoubleToInt64Bits(s1));
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}
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opcode |= ((size & 3) << 8);
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int fpscr = (int)rMode << (int)Fpcr.RMode;
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, fpscr: fpscr);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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