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https://github.com/Ryujinx/Ryujinx.git
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Add Sli_S/V & Sri_S/V inst.s (fast & slow paths), with Tests. (#797)
* Add Sli & Sri. * Add scalar variants.
This commit is contained in:
parent
86b42f176a
commit
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@ -437,6 +437,7 @@ namespace ARMeilleure.Decoders
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SetA64("0x101110<<100001001110xxxxxxxxxx", InstName.Shll_V, InstEmit.Shll_V, typeof(OpCodeSimd));
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SetA64("0x101110<<100001001110xxxxxxxxxx", InstName.Shll_V, InstEmit.Shll_V, typeof(OpCodeSimd));
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SetA64("0x00111100>>>xxx100001xxxxxxxxxx", InstName.Shrn_V, InstEmit.Shrn_V, typeof(OpCodeSimdShImm));
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SetA64("0x00111100>>>xxx100001xxxxxxxxxx", InstName.Shrn_V, InstEmit.Shrn_V, typeof(OpCodeSimdShImm));
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SetA64("0x001110<<1xxxxx001001xxxxxxxxxx", InstName.Shsub_V, InstEmit.Shsub_V, typeof(OpCodeSimdReg));
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SetA64("0x001110<<1xxxxx001001xxxxxxxxxx", InstName.Shsub_V, InstEmit.Shsub_V, typeof(OpCodeSimdReg));
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SetA64("0111111101xxxxxx010101xxxxxxxxxx", InstName.Sli_S, InstEmit.Sli_S, typeof(OpCodeSimdShImm));
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SetA64("0x10111100>>>xxx010101xxxxxxxxxx", InstName.Sli_V, InstEmit.Sli_V, typeof(OpCodeSimdShImm));
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SetA64("0x10111100>>>xxx010101xxxxxxxxxx", InstName.Sli_V, InstEmit.Sli_V, typeof(OpCodeSimdShImm));
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SetA64("0110111101xxxxxx010101xxxxxxxxxx", InstName.Sli_V, InstEmit.Sli_V, typeof(OpCodeSimdShImm));
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SetA64("0110111101xxxxxx010101xxxxxxxxxx", InstName.Sli_V, InstEmit.Sli_V, typeof(OpCodeSimdShImm));
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SetA64("0x001110<<1xxxxx011001xxxxxxxxxx", InstName.Smax_V, InstEmit.Smax_V, typeof(OpCodeSimdReg));
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SetA64("0x001110<<1xxxxx011001xxxxxxxxxx", InstName.Smax_V, InstEmit.Smax_V, typeof(OpCodeSimdReg));
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@ -485,6 +486,9 @@ namespace ARMeilleure.Decoders
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SetA64("01111110<<100001001010xxxxxxxxxx", InstName.Sqxtun_S, InstEmit.Sqxtun_S, typeof(OpCodeSimd));
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SetA64("01111110<<100001001010xxxxxxxxxx", InstName.Sqxtun_S, InstEmit.Sqxtun_S, typeof(OpCodeSimd));
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SetA64("0x101110<<100001001010xxxxxxxxxx", InstName.Sqxtun_V, InstEmit.Sqxtun_V, typeof(OpCodeSimd));
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SetA64("0x101110<<100001001010xxxxxxxxxx", InstName.Sqxtun_V, InstEmit.Sqxtun_V, typeof(OpCodeSimd));
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SetA64("0x001110<<1xxxxx000101xxxxxxxxxx", InstName.Srhadd_V, InstEmit.Srhadd_V, typeof(OpCodeSimdReg));
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SetA64("0x001110<<1xxxxx000101xxxxxxxxxx", InstName.Srhadd_V, InstEmit.Srhadd_V, typeof(OpCodeSimdReg));
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SetA64("0111111101xxxxxx010001xxxxxxxxxx", InstName.Sri_S, InstEmit.Sri_S, typeof(OpCodeSimdShImm));
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SetA64("0x10111100>>>xxx010001xxxxxxxxxx", InstName.Sri_V, InstEmit.Sri_V, typeof(OpCodeSimdShImm));
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SetA64("0110111101xxxxxx010001xxxxxxxxxx", InstName.Sri_V, InstEmit.Sri_V, typeof(OpCodeSimdShImm));
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SetA64("0>001110<<1xxxxx010101xxxxxxxxxx", InstName.Srshl_V, InstEmit.Srshl_V, typeof(OpCodeSimdReg));
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SetA64("0>001110<<1xxxxx010101xxxxxxxxxx", InstName.Srshl_V, InstEmit.Srshl_V, typeof(OpCodeSimdReg));
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SetA64("0101111101xxxxxx001001xxxxxxxxxx", InstName.Srshr_S, InstEmit.Srshr_S, typeof(OpCodeSimdShImm));
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SetA64("0101111101xxxxxx001001xxxxxxxxxx", InstName.Srshr_S, InstEmit.Srshr_S, typeof(OpCodeSimdShImm));
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SetA64("0x00111100>>>xxx001001xxxxxxxxxx", InstName.Srshr_V, InstEmit.Srshr_V, typeof(OpCodeSimdShImm));
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SetA64("0x00111100>>>xxx001001xxxxxxxxxx", InstName.Srshr_V, InstEmit.Srshr_V, typeof(OpCodeSimdShImm));
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@ -22,6 +22,11 @@ namespace ARMeilleure.Instructions
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13L << 56 | 12L << 48 | 09L << 40 | 08L << 32 | 05L << 24 | 04L << 16 | 01L << 8 | 00L << 0,
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13L << 56 | 12L << 48 | 09L << 40 | 08L << 32 | 05L << 24 | 04L << 16 | 01L << 8 | 00L << 0,
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11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0
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11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0
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};
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};
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private static readonly long[] _masks_SliSri = new long[] // Replication masks.
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{
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0x0101010101010101L, 0x0001000100010001L, 0x0000000100000001L, 0x0000000000000001L
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};
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#endregion
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#endregion
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public static void Rshrn_V(ArmEmitterContext context)
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public static void Rshrn_V(ArmEmitterContext context)
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@ -66,7 +71,7 @@ namespace ARMeilleure.Instructions
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res = context.AddIntrinsic(movInst, dLow, res);
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res = context.AddIntrinsic(movInst, dLow, res);
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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}
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else
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else
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{
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{
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@ -106,7 +111,7 @@ namespace ARMeilleure.Instructions
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}
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}
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else
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else
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{
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{
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EmitVectorUnaryOpZx(context, (op1) => context.ShiftLeft(op1, Const(shift)));
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EmitVectorUnaryOpZx(context, (op1) => context.ShiftLeft(op1, Const(shift)));
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}
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}
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}
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}
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@ -149,8 +154,6 @@ namespace ARMeilleure.Instructions
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int shift = GetImmShr(op);
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int shift = GetImmShr(op);
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long roundConst = 1L << (shift - 1);
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Operand d = GetVec(op.Rd);
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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Operand n = GetVec(op.Rn);
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@ -170,7 +173,7 @@ namespace ARMeilleure.Instructions
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res = context.AddIntrinsic(movInst, dLow, res);
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res = context.AddIntrinsic(movInst, dLow, res);
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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}
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else
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else
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{
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{
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@ -178,34 +181,14 @@ namespace ARMeilleure.Instructions
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}
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}
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}
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}
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public static void Sli_S(ArmEmitterContext context)
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{
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EmitSli(context, scalar: true);
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}
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public static void Sli_V(ArmEmitterContext context)
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public static void Sli_V(ArmEmitterContext context)
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{
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{
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OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
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EmitSli(context, scalar: false);
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Operand res = context.VectorZero();
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int elems = op.GetBytesCount() >> op.Size;
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int shift = GetImmShl(op);
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ulong mask = shift != 0 ? ulong.MaxValue >> (64 - shift) : 0;
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for (int index = 0; index < elems; index++)
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{
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Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
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Operand neShifted = context.ShiftLeft(ne, Const(shift));
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Operand de = EmitVectorExtractZx(context, op.Rd, index, op.Size);
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Operand deMasked = context.BitwiseAnd(de, Const(mask));
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Operand e = context.BitwiseOr(neShifted, deMasked);
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res = EmitVectorInsert(context, res, e, index, op.Size);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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}
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public static void Sqrshl_V(ArmEmitterContext context)
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public static void Sqrshl_V(ArmEmitterContext context)
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@ -290,6 +273,16 @@ namespace ARMeilleure.Instructions
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EmitShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.VectorSxZx);
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EmitShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.VectorSxZx);
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}
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}
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public static void Sri_S(ArmEmitterContext context)
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{
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EmitSri(context, scalar: true);
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}
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public static void Sri_V(ArmEmitterContext context)
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{
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EmitSri(context, scalar: false);
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}
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public static void Srshl_V(ArmEmitterContext context)
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public static void Srshl_V(ArmEmitterContext context)
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{
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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@ -395,7 +388,7 @@ namespace ARMeilleure.Instructions
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res = context.VectorZeroUpper64(res);
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res = context.VectorZeroUpper64(res);
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}
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}
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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}
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else
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else
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{
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{
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@ -690,7 +683,7 @@ namespace ARMeilleure.Instructions
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res = context.VectorZeroUpper64(res);
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res = context.VectorZeroUpper64(res);
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}
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}
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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}
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else
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else
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{
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{
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@ -1053,5 +1046,116 @@ namespace ARMeilleure.Instructions
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context.Copy(GetVec(op.Rd), res);
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context.Copy(GetVec(op.Rd), res);
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}
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}
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private static void EmitSli(ArmEmitterContext context, bool scalar)
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{
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OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
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int shift = GetImmShl(op);
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ulong mask = shift != 0 ? ulong.MaxValue >> (64 - shift) : 0UL;
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if (Optimizations.UseSse2 && op.Size > 0)
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{
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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Intrinsic sllInst = X86PsllInstruction[op.Size];
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Operand nShifted = context.AddIntrinsic(sllInst, n, Const(shift));
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Operand dMask = X86GetAllElements(context, (long)mask * _masks_SliSri[op.Size]);
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Operand dMasked = context.AddIntrinsic(Intrinsic.X86Pand, d, dMask);
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Operand res = context.AddIntrinsic(Intrinsic.X86Por, nShifted, dMasked);
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if ((op.RegisterSize == RegisterSize.Simd64) || scalar)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(d, res);
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}
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else
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{
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Operand res = context.VectorZero();
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int elems = !scalar ? op.GetBytesCount() >> op.Size : 1;
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for (int index = 0; index < elems; index++)
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{
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Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
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Operand neShifted = context.ShiftLeft(ne, Const(shift));
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Operand de = EmitVectorExtractZx(context, op.Rd, index, op.Size);
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Operand deMasked = context.BitwiseAnd(de, Const(mask));
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Operand e = context.BitwiseOr(neShifted, deMasked);
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res = EmitVectorInsert(context, res, e, index, op.Size);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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}
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private static void EmitSri(ArmEmitterContext context, bool scalar)
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{
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OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
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int shift = GetImmShr(op);
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int eSize = 8 << op.Size;
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ulong mask = (ulong.MaxValue << (eSize - shift)) & (ulong.MaxValue >> (64 - eSize));
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if (Optimizations.UseSse2 && op.Size > 0)
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{
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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Intrinsic srlInst = X86PsrlInstruction[op.Size];
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Operand nShifted = context.AddIntrinsic(srlInst, n, Const(shift));
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Operand dMask = X86GetAllElements(context, (long)mask * _masks_SliSri[op.Size]);
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Operand dMasked = context.AddIntrinsic(Intrinsic.X86Pand, d, dMask);
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Operand res = context.AddIntrinsic(Intrinsic.X86Por, nShifted, dMasked);
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if ((op.RegisterSize == RegisterSize.Simd64) || scalar)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(d, res);
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}
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else
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{
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Operand res = context.VectorZero();
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int elems = !scalar ? op.GetBytesCount() >> op.Size : 1;
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for (int index = 0; index < elems; index++)
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{
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Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
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Operand neShifted = shift != 64 ? context.ShiftRightUI(ne, Const(shift)) : Const(0UL);
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Operand de = EmitVectorExtractZx(context, op.Rd, index, op.Size);
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Operand deMasked = context.BitwiseAnd(de, Const(mask));
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Operand e = context.BitwiseOr(neShifted, deMasked);
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res = EmitVectorInsert(context, res, e, index, op.Size);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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}
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}
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}
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}
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}
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Shll_V,
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Shll_V,
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Shrn_V,
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Shrn_V,
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Shsub_V,
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Shsub_V,
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Sli_S,
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Sli_V,
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Sli_V,
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Smax_V,
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Smax_V,
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Smaxp_V,
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Smaxp_V,
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Sqxtun_S,
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Sqxtun_S,
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Sqxtun_V,
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Sqxtun_V,
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Srhadd_V,
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Srhadd_V,
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Sri_S,
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Sri_V,
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Srshl_V,
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Srshl_V,
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Srshr_S,
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Srshr_S,
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Srshr_V,
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Srshr_V,
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@ -218,7 +218,7 @@ namespace Ryujinx.Tests.Cpu
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return new uint[]
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return new uint[]
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{
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{
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0x5F405400u, // SHL D0, D0, #0
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0x5F405400u, // SHL D0, D0, #0
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//0x7F405400u // SLI D0, D0, #0
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0x7F405400u // SLI D0, D0, #0
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};
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};
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}
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}
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@ -285,10 +285,11 @@ namespace Ryujinx.Tests.Cpu
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};
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};
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}
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}
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private static uint[] _ShrImm_S_D_()
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private static uint[] _ShrImm_Sri_S_D_()
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{
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{
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return new uint[]
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return new uint[]
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{
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{
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0x7F404400u, // SRI D0, D0, #64
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0x5F402400u, // SRSHR D0, D0, #64
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0x5F402400u, // SRSHR D0, D0, #64
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0x5F403400u, // SRSRA D0, D0, #64
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0x5F403400u, // SRSRA D0, D0, #64
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0x5F400400u, // SSHR D0, D0, #64
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0x5F400400u, // SSHR D0, D0, #64
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@ -300,10 +301,11 @@ namespace Ryujinx.Tests.Cpu
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};
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};
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}
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}
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private static uint[] _ShrImm_V_8B_16B_()
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private static uint[] _ShrImm_Sri_V_8B_16B_()
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{
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{
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return new uint[]
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return new uint[]
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{
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{
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0x2F084400u, // SRI V0.8B, V0.8B, #8
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0x0F082400u, // SRSHR V0.8B, V0.8B, #8
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0x0F082400u, // SRSHR V0.8B, V0.8B, #8
|
||||||
0x0F083400u, // SRSRA V0.8B, V0.8B, #8
|
0x0F083400u, // SRSRA V0.8B, V0.8B, #8
|
||||||
0x0F080400u, // SSHR V0.8B, V0.8B, #8
|
0x0F080400u, // SSHR V0.8B, V0.8B, #8
|
||||||
@ -315,10 +317,11 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
};
|
};
|
||||||
}
|
}
|
||||||
|
|
||||||
private static uint[] _ShrImm_V_4H_8H_()
|
private static uint[] _ShrImm_Sri_V_4H_8H_()
|
||||||
{
|
{
|
||||||
return new uint[]
|
return new uint[]
|
||||||
{
|
{
|
||||||
|
0x2F104400u, // SRI V0.4H, V0.4H, #16
|
||||||
0x0F102400u, // SRSHR V0.4H, V0.4H, #16
|
0x0F102400u, // SRSHR V0.4H, V0.4H, #16
|
||||||
0x0F103400u, // SRSRA V0.4H, V0.4H, #16
|
0x0F103400u, // SRSRA V0.4H, V0.4H, #16
|
||||||
0x0F100400u, // SSHR V0.4H, V0.4H, #16
|
0x0F100400u, // SSHR V0.4H, V0.4H, #16
|
||||||
@ -330,10 +333,11 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
};
|
};
|
||||||
}
|
}
|
||||||
|
|
||||||
private static uint[] _ShrImm_V_2S_4S_()
|
private static uint[] _ShrImm_Sri_V_2S_4S_()
|
||||||
{
|
{
|
||||||
return new uint[]
|
return new uint[]
|
||||||
{
|
{
|
||||||
|
0x2F204400u, // SRI V0.2S, V0.2S, #32
|
||||||
0x0F202400u, // SRSHR V0.2S, V0.2S, #32
|
0x0F202400u, // SRSHR V0.2S, V0.2S, #32
|
||||||
0x0F203400u, // SRSRA V0.2S, V0.2S, #32
|
0x0F203400u, // SRSRA V0.2S, V0.2S, #32
|
||||||
0x0F200400u, // SSHR V0.2S, V0.2S, #32
|
0x0F200400u, // SSHR V0.2S, V0.2S, #32
|
||||||
@ -345,10 +349,11 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
};
|
};
|
||||||
}
|
}
|
||||||
|
|
||||||
private static uint[] _ShrImm_V_2D_()
|
private static uint[] _ShrImm_Sri_V_2D_()
|
||||||
{
|
{
|
||||||
return new uint[]
|
return new uint[]
|
||||||
{
|
{
|
||||||
|
0x6F404400u, // SRI V0.2D, V0.2D, #64
|
||||||
0x4F402400u, // SRSHR V0.2D, V0.2D, #64
|
0x4F402400u, // SRSHR V0.2D, V0.2D, #64
|
||||||
0x4F403400u, // SRSRA V0.2D, V0.2D, #64
|
0x4F403400u, // SRSRA V0.2D, V0.2D, #64
|
||||||
0x4F400400u, // SSHR V0.2D, V0.2D, #64
|
0x4F400400u, // SSHR V0.2D, V0.2D, #64
|
||||||
@ -743,12 +748,12 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Pairwise]
|
[Test, Pairwise]
|
||||||
public void ShrImm_S_D([ValueSource("_ShrImm_S_D_")] uint opcodes,
|
public void ShrImm_Sri_S_D([ValueSource("_ShrImm_Sri_S_D_")] uint opcodes,
|
||||||
[Values(0u)] uint rd,
|
[Values(0u)] uint rd,
|
||||||
[Values(1u, 0u)] uint rn,
|
[Values(1u, 0u)] uint rn,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
||||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntShift)] uint shift)
|
[Values(1u, 64u)] [Random(2u, 63u, RndCntShift)] uint shift)
|
||||||
{
|
{
|
||||||
uint immHb = (128 - shift) & 0x7F;
|
uint immHb = (128 - shift) & 0x7F;
|
||||||
|
|
||||||
@ -764,13 +769,13 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Pairwise]
|
[Test, Pairwise]
|
||||||
public void ShrImm_V_8B_16B([ValueSource("_ShrImm_V_8B_16B_")] uint opcodes,
|
public void ShrImm_Sri_V_8B_16B([ValueSource("_ShrImm_Sri_V_8B_16B_")] uint opcodes,
|
||||||
[Values(0u)] uint rd,
|
[Values(0u)] uint rd,
|
||||||
[Values(1u, 0u)] uint rn,
|
[Values(1u, 0u)] uint rn,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
||||||
[Values(1u, 8u)] [Random(2u, 7u, RndCntShift)] uint shift,
|
[Values(1u, 8u)] [Random(2u, 7u, RndCntShift)] uint shift,
|
||||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||||
{
|
{
|
||||||
uint immHb = (16 - shift) & 0x7F;
|
uint immHb = (16 - shift) & 0x7F;
|
||||||
|
|
||||||
@ -787,13 +792,13 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Pairwise]
|
[Test, Pairwise]
|
||||||
public void ShrImm_V_4H_8H([ValueSource("_ShrImm_V_4H_8H_")] uint opcodes,
|
public void ShrImm_Sri_V_4H_8H([ValueSource("_ShrImm_Sri_V_4H_8H_")] uint opcodes,
|
||||||
[Values(0u)] uint rd,
|
[Values(0u)] uint rd,
|
||||||
[Values(1u, 0u)] uint rn,
|
[Values(1u, 0u)] uint rn,
|
||||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
||||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
||||||
[Values(1u, 16u)] [Random(2u, 15u, RndCntShift)] uint shift,
|
[Values(1u, 16u)] [Random(2u, 15u, RndCntShift)] uint shift,
|
||||||
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
|
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
|
||||||
{
|
{
|
||||||
uint immHb = (32 - shift) & 0x7F;
|
uint immHb = (32 - shift) & 0x7F;
|
||||||
|
|
||||||
@ -810,13 +815,13 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Pairwise]
|
[Test, Pairwise]
|
||||||
public void ShrImm_V_2S_4S([ValueSource("_ShrImm_V_2S_4S_")] uint opcodes,
|
public void ShrImm_Sri_V_2S_4S([ValueSource("_ShrImm_Sri_V_2S_4S_")] uint opcodes,
|
||||||
[Values(0u)] uint rd,
|
[Values(0u)] uint rd,
|
||||||
[Values(1u, 0u)] uint rn,
|
[Values(1u, 0u)] uint rn,
|
||||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
||||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
||||||
[Values(1u, 32u)] [Random(2u, 31u, RndCntShift)] uint shift,
|
[Values(1u, 32u)] [Random(2u, 31u, RndCntShift)] uint shift,
|
||||||
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
||||||
{
|
{
|
||||||
uint immHb = (64 - shift) & 0x7F;
|
uint immHb = (64 - shift) & 0x7F;
|
||||||
|
|
||||||
@ -833,12 +838,12 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Pairwise]
|
[Test, Pairwise]
|
||||||
public void ShrImm_V_2D([ValueSource("_ShrImm_V_2D_")] uint opcodes,
|
public void ShrImm_Sri_V_2D([ValueSource("_ShrImm_Sri_V_2D_")] uint opcodes,
|
||||||
[Values(0u)] uint rd,
|
[Values(0u)] uint rd,
|
||||||
[Values(1u, 0u)] uint rn,
|
[Values(1u, 0u)] uint rn,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
||||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntShift)] uint shift)
|
[Values(1u, 64u)] [Random(2u, 63u, RndCntShift)] uint shift)
|
||||||
{
|
{
|
||||||
uint immHb = (128 - shift) & 0x7F;
|
uint immHb = (128 - shift) & 0x7F;
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user