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Add EXT, CMTST (vector) and UMULL (vector) instructions
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@ -142,11 +142,13 @@ namespace ChocolArm64
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Set("0>101110<<1xxxxx001111xxxxxxxxxx", AInstEmit.Cmhs_V, typeof(AOpCodeSimdReg));
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Set("0>101110<<100000100110xxxxxxxxxx", AInstEmit.Cmle_V, typeof(AOpCodeSimd));
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Set("0>001110<<100000101010xxxxxxxxxx", AInstEmit.Cmlt_V, typeof(AOpCodeSimd));
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Set("0>001110<<1xxxxx100011xxxxxxxxxx", AInstEmit.Cmtst_V, typeof(AOpCodeSimdReg));
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Set("0x00111000100000010110xxxxxxxxxx", AInstEmit.Cnt_V, typeof(AOpCodeSimd));
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Set("0x001110000xxxxx000011xxxxxxxxxx", AInstEmit.Dup_Gp, typeof(AOpCodeSimdIns));
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Set("01011110000xxxxx000001xxxxxxxxxx", AInstEmit.Dup_S, typeof(AOpCodeSimdIns));
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Set("0x001110000xxxxx000001xxxxxxxxxx", AInstEmit.Dup_V, typeof(AOpCodeSimdIns));
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Set("0x101110001xxxxx000111xxxxxxxxxx", AInstEmit.Eor_V, typeof(AOpCodeSimdReg));
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Set("0>101110000xxxxx0<xxx0xxxxxxxxxx", AInstEmit.Ext_V, typeof(AOpCodeSimdExt));
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Set("011111101x1xxxxx110101xxxxxxxxxx", AInstEmit.Fabd_S, typeof(AOpCodeSimdReg));
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Set("000111100x100000110000xxxxxxxxxx", AInstEmit.Fabs_S, typeof(AOpCodeSimd));
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Set("000111100x1xxxxx001010xxxxxxxxxx", AInstEmit.Fadd_S, typeof(AOpCodeSimdReg));
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@ -262,6 +264,7 @@ namespace ChocolArm64
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Set("011111100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_S, typeof(AOpCodeSimd));
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Set("0x1011100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_V, typeof(AOpCodeSimd));
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Set("0x001110000xxxxx001111xxxxxxxxxx", AInstEmit.Umov_S, typeof(AOpCodeSimdIns));
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Set("0x101110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Umull_V, typeof(AOpCodeSimdReg));
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Set("0>101110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Ushl_V, typeof(AOpCodeSimdReg));
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Set("0x10111100>>>xxx101001xxxxxxxxxx", AInstEmit.Ushll_V, typeof(AOpCodeSimdShImm));
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Set("011111110>>>>xxx000001xxxxxxxxxx", AInstEmit.Ushr_S, typeof(AOpCodeSimdShImm));
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14
ChocolArm64/Decoder/AOpCodeSimdExt.cs
Normal file
14
ChocolArm64/Decoder/AOpCodeSimdExt.cs
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@ -0,0 +1,14 @@
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using ChocolArm64.Instruction;
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namespace ChocolArm64.Decoder
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{
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class AOpCodeSimdExt : AOpCodeSimdReg
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{
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public int Imm4 { get; private set; }
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public AOpCodeSimdExt(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
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{
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int Imm4 = (OpCode >> 11) & 0xf;
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}
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}
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}
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@ -406,5 +406,10 @@ namespace ChocolArm64.Instruction
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{
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EmitVectorWidenRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
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}
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public static void Umull_V(AILEmitterCtx Context)
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{
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EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
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}
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}
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}
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@ -46,6 +46,45 @@ namespace ChocolArm64.Instruction
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EmitVectorCmp(Context, OpCodes.Blt_S);
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}
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public static void Cmtst_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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ulong SzMask = ulong.MaxValue >> (64 - (8 << Op.Size));
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size);
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EmitVectorExtractZx(Context, Op.Rm, Index, Op.Size);
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AILLabel LblTrue = new AILLabel();
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AILLabel LblEnd = new AILLabel();
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Context.Emit(OpCodes.And);
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Context.EmitLdc_I4(0);
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Context.Emit(OpCodes.Bne_Un_S, LblTrue);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size, 0);
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Context.Emit(OpCodes.Br_S, LblEnd);
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Context.MarkLabel(LblTrue);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size, (long)SzMask);
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Context.MarkLabel(LblEnd);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Fccmp_S(AILEmitterCtx Context)
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{
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AOpCodeSimdFcond Op = (AOpCodeSimdFcond)Context.CurrOp;
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@ -57,6 +57,31 @@ namespace ChocolArm64.Instruction
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}
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}
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public static void Ext_V(AILEmitterCtx Context)
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{
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AOpCodeSimdExt Op = (AOpCodeSimdExt)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < Bytes; Index++)
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{
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int Position = Op.Imm4 + Index;
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int Reg = Position < Bytes ? Op.Rn : Op.Rm;
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Position &= Bytes - 1;
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EmitVectorExtractZx(Context, Reg, Position, 0);
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EmitVectorInsert(Context, Op.Rd, Index, 0);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Fcsel_S(AILEmitterCtx Context)
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{
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AOpCodeSimdFcond Op = (AOpCodeSimdFcond)Context.CurrOp;
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