Commit Graph

168 Commits

Author SHA1 Message Date
gdkchan
932224f051 ARM exclusive monitor and multicore fixes (#589)
* Implement ARM exclusive load/store with compare exchange insts, and enable multicore by default

* Fix comment typo

* Support Linux and OSX on MemoryAlloc and CompareExchange128, some cleanup

* Use intel syntax on assembly code

* Adjust identation

* Add CPUID check and fix exclusive reservation granule size

* Update schema multicore scheduling default value

* Make the cpu id check code lower case aswell
2019-02-19 10:52:06 +11:00
gdkchan
948a758270 Optimize CMN/ADDS to do a single comparision like CMP/SUBS (#576) 2019-02-18 15:17:34 +11:00
gdkchan
a694420d11
Implement speculative translation on the CPU (#515)
* Implement speculative translation on the cpu, and change the way how branches to unknown or untranslated addresses works

* Port t0opt changes and other cleanups

* Change namespace from translation related classes to ChocolArm64.Translation, other minor tweaks

* Fix typo

* Translate higher quality code for indirect jumps aswell, and on some cases that were missed when lower quality (tier 0) code was available

* Remove debug print

* Remove direct argument passing optimization, and enable tail calls for BR instructions

* Call delegates directly with Callvirt rather than calling Execute, do not emit calls for tier 0 code

* Remove unused property

* Rename argument on ArmSubroutine delegate
2019-02-04 18:26:05 -03:00
gdkchan
c1bdf19061
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)

* Rename some opcode classes and flag masks for consistency

* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations

* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC

* Re-align arm32 instructions on the opcode table
2019-01-29 13:06:11 -03:00
LDj3SNuD
8f7fcede7f Add Smlal_Ve, Smlsl_Ve, Smull_Ve, Umlal_Ve, Umlsl_Ve, Umull_Ve Inst.; add Tests. Add Sse Opt. for Trn1/2_V and Uzp1/2_V Inst. Nits. (#566)
* Update OpCodeTable.cs

* Update InstEmitSimdArithmetic.cs

* Update InstEmitSimdHelper.cs

* Update CpuTestSimdRegElem.cs

* Update InstEmitSimdMove.cs

* Update InstEmitSimdCvt.cs

* Update SoftFallback.cs

* Update InstEmitSimdHelper.cs

* Update SoftFloat.cs

* Update CryptoHelper.cs

* Update InstEmitSimdArithmetic.cs

* Update InstEmitSimdCmp.cs

* Address PR feedback.

* Address PR feedback.
2019-01-29 10:54:39 -03:00
gdkchan
36b9ab0e48
Add ARM32 support on the translator (#561)
* Remove ARM32 interpreter and add ARM32 support on the translator

* Nits.

* Rename Cond -> Condition

* Align code again

* Rename Data to Alu

* Enable ARM32 support and handle undefined instructions

* Use the IsThumb method to check if its a thumb opcode

* Remove another 32-bits check
2019-01-24 23:59:53 -02:00
LDj3SNuD
0f5b6dfbe8 Fix Frecpe_S/V and Frsqrte_S/V (full FP emu.). Add Sse Opt. & SoftFloat Impl. for Fcmeq/ge/gt/le/lt_S/V (Reg & Zero), Faddp_S/V, Fmaxp_V, Fminp_V Inst.; add Sse Opt. for Shll_V, S/Ushll_V Inst.; improve Sse Opt. for Xtn_V Inst.. Add Tests. (#543)
* Update Optimizations.cs

* Update InstEmitSimdShift.cs

* Update InstEmitSimdHelper.cs

* Update InstEmitSimdArithmetic.cs

* Update InstEmitSimdMove.cs

* Update SoftFloat.cs

* Update InstEmitSimdCmp.cs

* Update CpuTestSimdShImm.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Nit.

* Update SoftFloat.cs

* Update InstEmitSimdArithmetic.cs

* Update InstEmitSimdHelper.cs

* Update CpuTestSimd.cs

* Explicit some implicit casts.

* Simplify some powers; nits.

* Update OpCodeTable.cs

* Update InstEmitSimdArithmetic.cs

* Update CpuTestSimdReg.cs

* Update InstEmitSimdArithmetic.cs
2018-12-26 15:11:36 -02:00
MS-DOS1999
6aaf9ccb53 Add Frintz_S/V opcode and unit test, correction of some unit tests (#523)
* Add Frintz_S/V opcode and unit test, correction of some unit tests

* --test

* fix code style issue

* delete tab
2018-12-17 22:29:47 -02:00
Roderick Sieben
2e143365eb Optimized memory modified check (#538)
* Optimized memory modified check

This was initially in some cases more expensive than plainly sending the data. Now it should have way better performance.

* Small refactoring

* renamed InvalidAccessEventArgs
* Renamed PtPageBits

* Removed ValueRange(set)

They are currently unused and won't be likely to be used in the near future
2018-12-11 23:48:54 -02:00
gdkchan
36e8e074c9
Misc. CPU improvements (#519)
* Fix and simplify TranslatorCache

* Fix some assignment alignments, remove some unused usings

* Changes to ILEmitter, separate it from ILEmitterCtx

* Rename ILEmitter to ILMethodBuilder

* Rename LdrLit and *_Fix opcodes

* Revert TranslatorCache impl to the more performant one, fix a few issues with it

* Allow EmitOpCode to be called even after everything has been emitted

* Make Emit and AdvanceOpCode private, simplify it a bit now that it starts emiting from the entry point

* Remove unneeded temp use

* Add missing exit call on TestExclusive

* Use better hash

* Implement the == and != operators
2018-12-10 22:58:52 -02:00
LDj3SNuD
ad00fd0244 Fix Sshl_V; Add S/Uqrshl_V, S/Uqshl_V, S/Urshl_V; Add Tests. (#516)
* Update OpCodeTable.cs

* Update InstEmitSimdShift.cs

* Update SoftFallback.cs

* Update CpuTestSimdReg.cs

* Nit.

* Update SoftFallback.cs

* Update Optimizations.cs

* Update InstEmitSimdLogical.cs

* Update InstEmitSimdArithmetic.cs
2018-12-01 22:34:43 -02:00
gdkchan
00579927e4
Better process implementation (#491)
* Initial implementation of KProcess

* Some improvements to the memory manager, implement back guest stack trace printing

* Better GetInfo implementation, improve checking in some places with information from process capabilities

* Allow the cpu to read/write from the correct memory locations for accesses crossing a page boundary

* Change long -> ulong for address/size on memory related methods to avoid unnecessary casts

* Attempt at implementing ldr:ro with new KProcess

* Allow BSS with size 0 on ldr:ro

* Add checking for memory block slab heap usage, return errors if full, exit gracefully

* Use KMemoryBlockSize const from KMemoryManager

* Allow all methods to read from non-contiguous locations

* Fix for TransactParcelAuto

* Address PR feedback, additionally fix some small issues related to the KIP loader and implement SVCs GetProcessId, GetProcessList, GetSystemInfo, CreatePort and ManageNamedPort

* Fix wrong check for source pages count from page list on MapPhysicalMemory

* Fix some issues with UnloadNro on ldr:ro
2018-11-28 20:18:09 -02:00
LDj3SNuD
e603b7afbc Add Sse Opt. for S/Umax_V, S/Umin_V, S/Uaddw_V, S/Usubw_V, Fabs_S/V, Fneg_S/V Inst.; for Fcvtl_V, Fcvtn_V Inst.; and for Fcmp_S Inst.. Add/Improve other Sse Opt.. Add Tests. (#496)
* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update InstEmitSimdCmp.cs

* Update SoftFloat.cs

* Update InstEmitAluHelper.cs

* Update InstEmitSimdArithmetic.cs

* Update InstEmitSimdHelper.cs

* Update VectorHelper.cs

* Update InstEmitSimdCvt.cs

* Update InstEmitSimdArithmetic.cs

* Update CpuTestSimd.cs

* Update InstEmitSimdArithmetic.cs

* Update OpCodeTable.cs

* Update InstEmitSimdArithmetic.cs

* Update InstEmitSimdCmp.cs

* Update InstEmitSimdCvt.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Create CpuTestSimdFcond.cs

* Update OpCodeTable.cs

* Update InstEmitSimdMove.cs

* Update CpuTestSimdIns.cs

* Create CpuTestSimdExt.cs

* Nit.

* Update PackageReference.
2018-11-18 00:41:16 -02:00
gdkchan
d2bb458b51 Improved GPU command lists decoding (#499)
* Better implementation of the DMA pusher, misc fixes

* Remove some debug code

* Correct RGBX8 format

* Add support for linked Texture Sampler Control

* Attempt to fix upside down screen issue
2018-11-17 05:01:31 +01:00
gdkchan
a4822b7946
Fix BLR when the source reg is X30 (#493) 2018-11-09 16:41:20 -02:00
LDj3SNuD
1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
* Update SoftFloat.cs

* Update SoftFallback.cs

* Update InstEmitSimdShift.cs

* Update InstEmitSimdCvt.cs

* Update InstEmitSimdArithmetic.cs

* Update CryptoHelper.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuThreadState.cs

* Update OpCodeTable.cs

* Add files via upload

* Nit.

* Remove unused using. Nit.

* Remove unused using. FZ update.

* Nit.

* Remove unused using.
2018-11-01 01:22:09 -03:00
Alex Barney
9cb57fb4bb Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)
* Change naming convention for Ryujinx project

* Change naming convention for ChocolArm64 project

* Fix NaN

* Remove unneeded this. from Ryujinx project

* Adjust naming from new PRs

* Name changes based on feedback

* How did this get removed?

* Rebasing fix

* Change FP enum case

* Remove prefix from ChocolArm64 classes - Part 1

* Remove prefix from ChocolArm64 classes - Part 2

* Fix alignment from last commit's renaming

* Rename namespaces

* Rename stragglers

* Fix alignment

* Rename OpCode class

* Missed a few

* Adjust alignment
2018-10-30 22:43:02 -03:00
gdkchan
5a87e58183 Fix regression caused by wrong time delta calculation on cache deletion methods 2018-10-30 11:42:27 -03:00
gdkchan
5b13ee655c
Fix the rotate right method on ABitUtils (#486) 2018-10-28 22:18:58 -03:00
jduncanator
c1b7340023 Timing: Optimize Timestamp Aquisition (#479)
* Timing: Optimize Timestamp Aquisition

Currently, we make use of Environment.TickCount in a number of places. This has some downsides, mainly being that the TickCount is a signed 32-bit integer, and has an effective limit of ~25 days before overflowing and wrapping around. Due to the signed-ness of the value, this also caused issues with negative numbers. This resolves these issues by using a 64-bit tick count obtained from Performance Counters (via the Stopwatch class). This has a beneficial side effect of being significantly more accurate than the TickCount.

* Timing: Rename ElapsedTicks to ElapsedMilliseconds and expose TicksPerX

* Timing: Some style changes

* Timing: Align static variable initialization
2018-10-28 19:31:13 -03:00
LDj3SNuD
b956bbc32c Add SHA1C, SHA1H, SHA1M, SHA1P, SHA1SU0, SHA1SU1 and Isb instructions; add 6 Tests (closed box). (#483)
* Update AOpCodeTable.cs

* Update AInstEmitSystem.cs

* Update AInstEmitSimdHash.cs

* Update ASoftFallback.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs
2018-10-28 19:27:50 -03:00
LDj3SNuD
00d4f44bbb Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480)
* Update AILEmitterCtx.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdShift.cs
2018-10-25 19:10:41 -03:00
LDj3SNuD
e674b37710 Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)
* Update CpuTest.cs

* Update CpuTestSimd.cs

* Superseded.

* Update AInstEmitSimdCvt.cs

* Update ASoftFloat.cs

* Nit.

* Update PackageReferences.

* Update AInstEmitSimdArithmetic.cs

* Update AVectorHelper.cs

* Update ASoftFloat.cs

* Update ASoftFallback.cs

* Update AThreadState.cs

* Create FPType.cs

* Create FPExc.cs

* Create FPCR.cs

* Create FPSR.cs

* Update ARoundMode.cs

* Update APState.cs

* Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover.

* Nits.
2018-10-23 11:12:45 -03:00
gdkchan
2cb8541462 Print stack trace on invalid memory accesses (#461)
* Print stack trace on invalid memory accesses

* Rebased, change code region base address for 39-bits address space, print stack trace on break and undefined instructions too
2018-10-20 22:07:52 +00:00
LDj3SNuD
894459fcd7 Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449)
* Update AOpCodeTable.cs

* Update AInstEmitSimdMove.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdShift.cs

* Update ASoftFallback.cs

* Update ASoftFloat.cs

* Update AOpCodeSimdRegElemF.cs

* Update CpuTestSimdIns.cs

* Update CpuTestSimdRegElem.cs

* Create CpuTestSimdRegElemF.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Superseded Fmul_Se Test. Nit.

* Address PR feedback.

* Address PR feedback.

* Update AInstEmitSimdArithmetic.cs

* Update ASoftFallback.cs

* Update AInstEmitAlu.cs

* Update AInstEmitSimdShift.cs
2018-10-13 23:35:16 -03:00
gdkchan
74ca82c534
Tweak cpu cache deletion policy values (#433)
* Tweak cpu cache deletion policy values

* Address PR feedback
2018-10-07 23:40:37 -03:00
LDj3SNuD
bba9bf97d0 Add 9+7 fast/slow FP inst. impls.; add 14 FP Tests. (#437)
* Update CpuTest.cs

* Delete CpuTestSimdCmp.cs

Obsolete.

* Update CpuTestSimdArithmetic.cs

Superseded.

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdHelper.cs

* Update ASoftFloat.cs

* Nit.

* Update AOpCodeTable.cs

* Update AOptimizations.cs

* Update AInstEmitSimdArithmetic.cs

* Update ASoftFloat.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update ASoftFloat.cs

* Update CpuTestSimdReg.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update ASoftFloat.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs
2018-10-05 22:45:59 -03:00
gdkchan
0b52ee6627
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
* Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics, some CQ improvements

* Remove useless space

* Address PR feedback

* Revert EmitVectorZero32_128 changes
2018-09-26 23:30:21 -03:00
gdkchan
54ed9096bd
Add FMAXP and FMINP (Vector) instructions on the CPU (#412)
* Add FMAXP and FMINP (Vector) instructions on the CPU

* Address PR feedback
2018-09-22 17:26:18 -03:00
gdkchan
6d65e53664
Remove cold methods from the CPU cache (#224)
* Remove unused tracing functionality from the CPU

* GetNsoExecutable -> GetExecutable

* Unsigned comparison

* Re-add cpu tracing

* Config change

* Remove cold methods from the translation cache on the cpu

* Replace lock with try lock, pass new ATranslatorCache instead of ATranslator

* Rebase fixups
2018-09-19 17:07:56 -03:00
gdkchan
99b2692425
Fix performance regression caused by the new scheduler changes (#422)
* Call interrupt less often, remove some leftovers from the old scheduler code

* Remove unneeded attribute
2018-09-19 12:16:20 -03:00
gdkchan
b8133c1997
Thread scheduler rewrite (#393)
* Started to rewrite the thread scheduler

* Add a single core-like scheduling mode, enabled by default

* Clear exclusive monitor on context switch

* Add SetThreadActivity, misc fixes

* Implement WaitForAddress and SignalToAddress svcs, misc fixes

* Misc fixes (on SetActivity and Arbiter), other tweaks

* Rebased

* Add missing null check

* Rename multicore key on config, fix UpdatePriorityInheritance

* Make scheduling data MLQs private

* nit: Ordering
2018-09-18 20:36:43 -03:00
gdkchan
d4187aaa9d
Allow "reinterpretation" of framebuffer/zeta formats (#418)
* (Re)Implement format reinterpretation, other changes

* Implement writeback to guest memory, some refactoring

* More refactoring, implement reinterpretation the old way again

* Clean up

* Some fixes on M2MF (old Dma engine), added partial support for P2MF, fix conditional ssy, add Z24S8 zeta format, other fixes

* nit: Formatting

* Address PR feedback
2018-09-18 01:30:35 -03:00
LDj3SNuD
c7387be0d2 Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. (#409)
* Update AOpCodeTable.cs

* Update AInstEmitSimdShift.cs

* Update CpuTestSimdShImm.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdHelper.cs

* Create CpuTestSimdIns.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuTest.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs
2018-09-17 01:54:05 -03:00
LDj3SNuD
a0c78f7920 Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407)
* Update AOpCodeTable.cs

* Update AInstEmitSimdShift.cs

* Update ASoftFallback.cs

* Update AOpCodeSimdShImm.cs

* Update ABitUtils.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdHelper.cs

* Create CpuTestSimdShImm.cs

* Create CpuTestSimdRegElem.cs

* Address PR feedback.

* Nit.

* Nit.
2018-09-08 14:24:29 -03:00
LDj3SNuD
42e4e02a64 Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390)
* Update AOpCodeTable.cs

* Update AInstEmitSimdCvt.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update CpuTestSimd.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Add QCFlagBit.

* Add QCFlagBit.
2018-09-01 11:52:51 -03:00
LDj3SNuD
68300368d7 Add SHADD, SHSUB, UHSUB, SRHADD, URHADD, instructions; add 12 Tests. (#380)
* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdCrypto.cs
2018-08-27 03:44:01 -03:00
LDj3SNuD
d021d5dfa9 Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365)
* Create CpuTestSimdCrypto.cs

* Update AOpCodeTable.cs

* Create AInstEmitSimdCrypto.cs

* Update ASoftFallback.cs

* Create ACryptoHelper.cs
2018-08-20 01:20:26 -03:00
LDj3SNuD
34100051e4 Add SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions; add 4 Tests (closed box). (#352)
* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update Bits.cs

* Update Integer.cs

* Update AOpCodeTable.cs

* Create AInstEmitSimdHash.cs

* Update ASoftFallback.cs
2018-08-16 21:44:44 -03:00
gdkchan
521751795a
Code style fixes and nits on the HLE project (#355)
* Some style fixes and nits on ITimeZoneService

* Remove some unneeded usings

* Remove the Ryujinx.HLE.OsHle.Handles namespace

* Remove hbmenu automatic load on process exit

* Rename Ns to Device, rename Os to System, rename SystemState to State

* Move Exceptions and Utilities out of OsHle

* Rename OsHle to HOS

* Rename OsHle folder to HOS

* IManagerDisplayService and ISystemDisplayService style fixes

* BsdError shouldn't be public

* Add a empty new line before using static

* Remove unused file

* Some style fixes on NPDM

* Exit gracefully when the application is closed

* Code style fixes on IGeneralService

* Add 0x prefix on values printed as hex

* Small improvements on finalization code

* Move ProcessId and ThreadId out of AThreadState

* Rename VFs to FileSystem

* FsAccessHeader shouldn't be public. Also fix file names casing

* More case changes on NPDM

* Remove unused files

* Move using to the correct place on NPDM

* Use properties on KernelAccessControlMmio

* Address PR feedback
2018-08-16 20:47:36 -03:00
gdkchan
c393cdf8e3
More flexible memory manager (#307)
* Keep track mapped buffers with fixed offsets

* Started rewriting the memory manager

* Initial support for MapPhysicalMemory and UnmapPhysicalMemory, other tweaks

* MapPhysicalMemory/UnmapPhysicalMemory support, other tweaks

* Rebased

* Optimize the map/unmap physical memory svcs

* Integrate shared font support

* Fix address space reserve alignment

* Some fixes related to gpu memory mapping

* Some cleanup

* Only try uploading const buffers that are really used

* Check if memory region is contiguous

* Rebased

* Add missing count increment on IsRegionModified

* Check for reads/writes outside of the address space, optimize translation with a tail call
2018-08-15 15:59:51 -03:00
gdkchan
55374ebba0
Zero out bits 63:32 of scalar float operations with SSE intrinsics (#273) 2018-08-14 23:54:12 -03:00
LDj3SNuD
4518c52c65 Add Sadalp_V, Saddlp_V, Uadalp_V, Uaddlp_V instructions; add 8 Tests. (#340)
* Update Instructions.cs

* Update CpuTestSimd.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs
2018-08-13 18:10:02 -03:00
LDj3SNuD
02a6fdcd13 Add Sqdmulh_S, Sqdmulh_V, Sqrdmulh_S, Sqrdmulh_V instructions; add 6 Tests. Now all saturating methods are on ASoftFallback. (#334)
* Update Instructions.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdHelper.cs

* Update ASoftFallback.cs

* Update CpuTestAlu.cs

* Update CpuTestAluImm.cs

* Update CpuTestAluRs.cs

* Update CpuTestAluRx.cs

* Update CpuTestBfm.cs

* Update CpuTestCcmpImm.cs

* Update CpuTestCcmpReg.cs

* Update CpuTestCsel.cs

* Update CpuTestMov.cs

* Update CpuTestMul.cs

* Update Ryujinx.Tests.csproj

* Update Ryujinx.csproj

* Update Luea.csproj

* Update Ryujinx.ShaderTools.csproj

* Address PR feedback (further tested).

* Address PR feedback.
2018-08-10 14:27:15 -03:00
gdkchan
267af1f0f7
Fix load/store exclusive/atomic pairwise instructions (#337) 2018-08-10 01:14:27 -03:00
gdkchan
3cf1b6cf77 Fix silly copy/paste error on float variant of the FMINNM instruction 2018-08-05 18:56:30 -03:00
gdkchan
221270db90
More accurate impl of FMINNM/FMAXNM, add vector variants (#296)
* More accurate impl of FMINNM/FMAXNM, add vector variants

* Optimize for the 0 case when op1 != op2

* Address PR feedback
2018-08-05 02:54:21 -03:00
LDj3SNuD
5f34353dce Add SQADD, UQADD, SQSUB, UQSUB, SUQADD, USQADD, SQABS, SQNEG (Scalar, Vector) instructions; add 24 Tests. Most saturation instructions now on ASoftFallback. (#314)
* Update AOpCodeTable.cs

* Update AInstEmitSimdHelper.cs

* Update AInstEmitSimdArithmetic.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update AInstEmitSimdHelper.cs

* Update AInstEmitSimdHelper.cs

* Update AInstEmitSimdHelper.cs

* Update AInstEmitSimdHelper.cs

* Update ASoftFallback.cs

* Update AInstEmitSimdHelper.cs

* Update ASoftFallback.cs

* Update AInstEmitSimdHelper.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update ASoftFallback.cs

* Update AInstEmitSimdHelper.cs

* Opt. (retest).
2018-08-04 16:58:54 -03:00
ReinUsesLisp
3208173620 Cache changes (#302)
* Skip repeated cache tests between same sync

* Skip some checks for regions where just one resource is resident

* Dehardcode residency page size

* Some cleanup
2018-07-29 01:39:15 -03:00
Arthur Chen
39d36145ba update encoding for branch instruction (#305) 2018-07-26 13:46:05 -03:00