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![Alex Barney](/assets/img/avatar_default.png)
* Fix typos * Remove unneeded using statements * Enforce var style more * Remove redundant qualifiers * Fix some indentation * Disable naming warnings on files with external enum names * Fix build * Mass find & replace for comments with no spacing * Standardize todo capitalization and for/if spacing
320 lines
8.7 KiB
C#
320 lines
8.7 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.IntermediateRepresentation;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using static ChocolArm64.Instructions.InstEmit32Helper;
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using static ChocolArm64.Instructions.InstEmitMemoryHelper;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit32
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{
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private const int ByteSizeLog2 = 0;
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private const int HWordSizeLog2 = 1;
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private const int WordSizeLog2 = 2;
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private const int DWordSizeLog2 = 3;
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[Flags]
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enum AccessType
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{
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Store = 0,
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Signed = 1,
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Load = 2,
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LoadZx = Load,
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LoadSx = Load | Signed,
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}
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public static void Ldm(ILEmitterCtx context)
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{
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OpCode32MemMult op = (OpCode32MemMult)context.CurrOp;
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EmitLoadFromRegister(context, op.Rn);
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bool writesToPc = (op.RegisterMask & (1 << RegisterAlias.Aarch32Pc)) != 0;
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bool writeBack = op.PostOffset != 0 && (op.Rn != RegisterAlias.Aarch32Pc || !writesToPc);
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if (writeBack)
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{
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context.Emit(OpCodes.Dup);
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}
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context.EmitLdc_I4(op.Offset);
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context.Emit(OpCodes.Add);
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context.EmitSttmp();
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if (writeBack)
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{
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context.EmitLdc_I4(op.PostOffset);
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context.Emit(OpCodes.Add);
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EmitStoreToRegister(context, op.Rn);
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}
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int mask = op.RegisterMask;
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int offset = 0;
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for (int register = 0; mask != 0; mask >>= 1, register++)
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{
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if ((mask & 1) != 0)
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{
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context.EmitLdtmp();
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context.EmitLdc_I4(offset);
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context.Emit(OpCodes.Add);
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EmitReadZxCall(context, WordSizeLog2);
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EmitStoreToRegister(context, register);
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offset += 4;
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}
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}
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}
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public static void Ldr(ILEmitterCtx context)
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{
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EmitLoadOrStore(context, WordSizeLog2, AccessType.LoadZx);
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}
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public static void Ldrb(ILEmitterCtx context)
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{
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EmitLoadOrStore(context, ByteSizeLog2, AccessType.LoadZx);
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}
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public static void Ldrd(ILEmitterCtx context)
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{
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EmitLoadOrStore(context, DWordSizeLog2, AccessType.LoadZx);
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}
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public static void Ldrh(ILEmitterCtx context)
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{
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EmitLoadOrStore(context, HWordSizeLog2, AccessType.LoadZx);
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}
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public static void Ldrsb(ILEmitterCtx context)
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{
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EmitLoadOrStore(context, ByteSizeLog2, AccessType.LoadSx);
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}
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public static void Ldrsh(ILEmitterCtx context)
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{
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EmitLoadOrStore(context, HWordSizeLog2, AccessType.LoadSx);
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}
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public static void Stm(ILEmitterCtx context)
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{
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OpCode32MemMult op = (OpCode32MemMult)context.CurrOp;
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EmitLoadFromRegister(context, op.Rn);
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context.EmitLdc_I4(op.Offset);
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context.Emit(OpCodes.Add);
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context.EmitSttmp();
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int mask = op.RegisterMask;
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int offset = 0;
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for (int register = 0; mask != 0; mask >>= 1, register++)
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{
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if ((mask & 1) != 0)
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{
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context.EmitLdtmp();
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context.EmitLdc_I4(offset);
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context.Emit(OpCodes.Add);
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EmitLoadFromRegister(context, register);
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EmitWriteCall(context, WordSizeLog2);
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// Note: If Rn is also specified on the register list,
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// and Rn is the first register on this list, then the
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// value that is written to memory is the unmodified value,
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// before the write back. If it is on the list, but it's
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// not the first one, then the value written to memory
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// varies between CPUs.
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if (offset == 0 && op.PostOffset != 0)
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{
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// Emit write back after the first write.
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EmitLoadFromRegister(context, op.Rn);
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context.EmitLdc_I4(op.PostOffset);
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context.Emit(OpCodes.Add);
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EmitStoreToRegister(context, op.Rn);
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}
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offset += 4;
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}
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}
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}
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public static void Str(ILEmitterCtx context)
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{
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EmitLoadOrStore(context, WordSizeLog2, AccessType.Store);
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}
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public static void Strb(ILEmitterCtx context)
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{
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EmitLoadOrStore(context, ByteSizeLog2, AccessType.Store);
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}
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public static void Strd(ILEmitterCtx context)
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{
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EmitLoadOrStore(context, DWordSizeLog2, AccessType.Store);
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}
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public static void Strh(ILEmitterCtx context)
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{
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EmitLoadOrStore(context, HWordSizeLog2, AccessType.Store);
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}
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private static void EmitLoadOrStore(ILEmitterCtx context, int size, AccessType accType)
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{
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OpCode32Mem op = (OpCode32Mem)context.CurrOp;
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if (op.Index || op.WBack)
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{
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EmitLoadFromRegister(context, op.Rn);
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context.EmitLdc_I4(op.Imm);
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context.Emit(op.Add ? OpCodes.Add : OpCodes.Sub);
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context.EmitSttmp();
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}
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if (op.Index)
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{
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context.EmitLdtmp();
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}
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else
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{
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EmitLoadFromRegister(context, op.Rn);
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}
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if ((accType & AccessType.Load) != 0)
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{
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if ((accType & AccessType.Signed) != 0)
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{
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EmitReadSx32Call(context, size);
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}
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else
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{
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EmitReadZxCall(context, size);
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}
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if (op.WBack)
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{
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context.EmitLdtmp();
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EmitStoreToRegister(context, op.Rn);
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}
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if (size == DWordSizeLog2)
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{
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context.Emit(OpCodes.Dup);
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context.EmitLdflg((int)PState.EBit);
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ILLabel lblBigEndian = new ILLabel();
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ILLabel lblEnd = new ILLabel();
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context.Emit(OpCodes.Brtrue_S, lblBigEndian);
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// Little endian mode.
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context.Emit(OpCodes.Conv_U4);
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EmitStoreToRegister(context, op.Rt);
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context.EmitLsr(32);
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context.Emit(OpCodes.Conv_U4);
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EmitStoreToRegister(context, op.Rt | 1);
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context.Emit(OpCodes.Br_S, lblEnd);
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// Big endian mode.
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context.MarkLabel(lblBigEndian);
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context.EmitLsr(32);
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context.Emit(OpCodes.Conv_U4);
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EmitStoreToRegister(context, op.Rt);
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context.Emit(OpCodes.Conv_U4);
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EmitStoreToRegister(context, op.Rt | 1);
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context.MarkLabel(lblEnd);
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}
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else
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{
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EmitStoreToRegister(context, op.Rt);
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}
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}
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else
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{
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if (op.WBack)
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{
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context.EmitLdtmp();
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EmitStoreToRegister(context, op.Rn);
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}
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EmitLoadFromRegister(context, op.Rt);
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if (size == DWordSizeLog2)
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{
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context.Emit(OpCodes.Conv_U8);
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context.EmitLdflg((int)PState.EBit);
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ILLabel lblBigEndian = new ILLabel();
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ILLabel lblEnd = new ILLabel();
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context.Emit(OpCodes.Brtrue_S, lblBigEndian);
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// Little endian mode.
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EmitLoadFromRegister(context, op.Rt | 1);
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context.Emit(OpCodes.Conv_U8);
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context.EmitLsl(32);
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context.Emit(OpCodes.Or);
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context.Emit(OpCodes.Br_S, lblEnd);
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// Big endian mode.
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context.MarkLabel(lblBigEndian);
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context.EmitLsl(32);
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EmitLoadFromRegister(context, op.Rt | 1);
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context.Emit(OpCodes.Conv_U8);
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context.Emit(OpCodes.Or);
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context.MarkLabel(lblEnd);
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}
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EmitWriteCall(context, size);
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}
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}
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}
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} |