Ryujinx/ChocolArm64/Instructions
gdkchan a731ab3a2a Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 21:56:22 +03:00
..
CryptoHelper.cs Add Smlal_Ve, Smlsl_Ve, Smull_Ve, Umlal_Ve, Umlsl_Ve, Umull_Ve Inst.; add Tests. Add Sse Opt. for Trn1/2_V and Uzp1/2_V Inst. Nits. (#566) 2019-01-29 10:54:39 -03:00
Inst.cs Add ARM32 support on the translator (#561) 2019-01-24 23:59:53 -02:00
InstEmit32Helper.cs Misc cleanup (#708) 2019-07-02 04:39:22 +02:00
InstEmitAlu32.cs Misc cleanup (#708) 2019-07-02 04:39:22 +02:00
InstEmitAlu.cs Misc cleanup (#708) 2019-07-02 04:39:22 +02:00
InstEmitAluHelper.cs Misc cleanup (#708) 2019-07-02 04:39:22 +02:00
InstEmitBfm.cs Misc cleanup (#708) 2019-07-02 04:39:22 +02:00
InstEmitCcmp.cs Refactoring and optimization on CPU translation (#661) 2019-04-26 14:55:12 +10:00
InstEmitCsel.cs Refactoring and optimization on CPU translation (#661) 2019-04-26 14:55:12 +10:00
InstEmitException.cs Misc cleanup (#708) 2019-07-02 04:39:22 +02:00
InstEmitFlow32.cs Misc cleanup (#708) 2019-07-02 04:39:22 +02:00
InstEmitFlow.cs Refactoring and optimization on CPU translation (#661) 2019-04-26 14:55:12 +10:00
InstEmitFlowHelper.cs Misc cleanup (#708) 2019-07-02 04:39:22 +02:00
InstEmitHash.cs Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) 2018-10-30 22:43:02 -03:00
InstEmitMemory32.cs Misc cleanup (#708) 2019-07-02 04:39:22 +02:00
InstEmitMemory.cs Misc cleanup (#708) 2019-07-02 04:39:22 +02:00
InstEmitMemoryEx.cs Misc cleanup (#708) 2019-07-02 04:39:22 +02:00
InstEmitMemoryHelper.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
InstEmitMove.cs Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) 2018-10-30 22:43:02 -03:00
InstEmitMul.cs Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) 2018-10-30 22:43:02 -03:00
InstEmitSimdArithmetic.cs Add Saddlv_V Inst. Improve Cnt_V, Dup_Gp & Ins_Gp Tests. Tuneup Cls_V & Clz_V Tests. (#720) 2019-07-08 11:55:37 -03:00
InstEmitSimdCmp.cs Refactoring and optimization on CPU translation (#661) 2019-04-26 14:55:12 +10:00
InstEmitSimdCrypto.cs Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) 2018-10-30 22:43:02 -03:00
InstEmitSimdCvt.cs Add FCVT <Hd>, <Sn> and FCVT <Sd>, <Hn> Inst.; add Tests. (#692) 2019-05-30 19:51:39 -03:00
InstEmitSimdHash.cs Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) 2018-10-30 22:43:02 -03:00
InstEmitSimdHelper.cs Add Saddlv_V Inst. Improve Cnt_V, Dup_Gp & Ins_Gp Tests. Tuneup Cls_V & Clz_V Tests. (#720) 2019-07-08 11:55:37 -03:00
InstEmitSimdLogical.cs Add Cmeq_V, Cmge_V, Cmgt_V, Cmle_V & Cmlt_V (Z & ~Z) Sse opt.. (#646) 2019-03-25 10:23:27 +11:00
InstEmitSimdMemory.cs Misc cleanup (#708) 2019-07-02 04:39:22 +02:00
InstEmitSimdMove.cs Implement the remaining tests for Simd and Fp instructions of data processing type. Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. (#709) 2019-06-29 20:02:48 -03:00
InstEmitSimdShift.cs Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614) 2019-03-13 19:23:52 +11:00
InstEmitSystem.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
InstEmitter.cs Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) 2018-10-30 22:43:02 -03:00
SoftFallback.cs Add Smlal_Ve, Smlsl_Ve, Smull_Ve, Umlal_Ve, Umlsl_Ve, Umull_Ve Inst.; add Tests. Add Sse Opt. for Trn1/2_V and Uzp1/2_V Inst. Nits. (#566) 2019-01-29 10:54:39 -03:00
SoftFloat.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
VectorHelper.cs Misc cleanup (#708) 2019-07-02 04:39:22 +02:00