mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-07-13 17:21:46 +02:00
d904706fc0
* Implement Jump Table for Native Calls NOTE: this slows down rejit considerably! Not recommended to be used without codegen optimisation or AOT. - Does not work on Linux - A32 needs an additional commit. * A32 Support (WIP) * Actually write Direct Call pointers to the table That would help. * Direct Calls: Rather than returning to the translator, attempt to keep within the native stack frame. A return to the translator can still happen, but only by exceptionally bubbling up to it. Also: - Always translate lowCq as a function. Faster interop with the direct jumps, and this will be useful in future if we want to do speculative translation. - Tail Call Detection: after the decoding stage, detect if we do a tail call, and avoid translating into it. Detected if a jump is made to an address outwith the contiguous sequence of blocks surrounding the entry point. The goal is to reduce code touched by jit and rejit. * A32 Support * Use smaller max function size for lowCq, fix exceptional returns When a return has an unexpected value and there is no code block following this one, we now return the value rather than continuing. * CompareAndSwap (buggy) * Ensure CompareAndSwap does not get optimized away. * Use CompareAndSwap to make the dynamic table thread safe. * Tail call for linux, throw on too many arguments. * Combine CompareAndSwap 128 and 32/64. They emit different IR instructions since their PreAllocator behaviour is different, but now they just have one function on EmitterContext. * Fix issues separating from optimisations. * Use a stub to find and execute missing functions. This allows us to skip doing many runtime comparisons and branches, and reduces the amount of code we need to emit significantly. For the indirect call table, this stub also does the work of moving in the highCq address to the table when one is found. * Make Jump Tables and Jit Cache dynmically resize Reserve virtual memory, commit as needed. * Move TailCallRemover to its own class. * Multithreaded Translation (based on heuristic) A poor one, at that. Need to get core count for a better one, which means a lot of OS specific garbage. * Better priority management for background threads. * Bound core limit a bit more Past a certain point the load is not paralellizable and starts stealing from the main thread. Likely due to GC, memory, heap allocation thread contention. Reduce by one core til optimisations come to improve the situation. * Fix memory management on linux. * Temporary solution to some sync problems. This will make sure threads exit correctly, most of the time. There is a potential race where setting the sync counter to 0 does nothing (counter stays at what it was before, thread could take too long to exit), but we need to find a better way to do this anyways. Synchronization frequency has been tightened as we never enter blockwise segments of code. Essentially this means, check every x functions or loop iterations, before lowcq blocks existed and were worth just as much. Ideally it should be done in a better way, since functions can be anywhere from 1 to 5000 instructions. (maybe based on host timer, or an interrupt flag from a scheduler thread) * Address feedback minus CompareAndSwap change. * Use default ReservedRegion granularity. * Merge CompareAndSwap with its V128 variant. * We already got the source, no need to do it again. * Make sure all background translation threads exit. * Fix CompareAndSwap128 Detection criteria was a bit scuffed. * Address Comments.
603 lines
20 KiB
C#
603 lines
20 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static class InstEmitAluHelper
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{
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public static void EmitNZFlagsCheck(ArmEmitterContext context, Operand d)
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{
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SetFlag(context, PState.NFlag, context.ICompareLess (d, Const(d.Type, 0)));
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SetFlag(context, PState.ZFlag, context.ICompareEqual(d, Const(d.Type, 0)));
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}
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public static void EmitAdcsCCheck(ArmEmitterContext context, Operand n, Operand d)
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{
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// C = (Rd == Rn && CIn) || Rd < Rn
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Operand cIn = GetFlag(PState.CFlag);
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Operand cOut = context.BitwiseAnd(context.ICompareEqual(d, n), cIn);
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cOut = context.BitwiseOr(cOut, context.ICompareLessUI(d, n));
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SetFlag(context, PState.CFlag, cOut);
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}
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public static void EmitAddsCCheck(ArmEmitterContext context, Operand n, Operand d)
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{
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// C = Rd < Rn
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SetFlag(context, PState.CFlag, context.ICompareLessUI(d, n));
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}
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public static void EmitAddsVCheck(ArmEmitterContext context, Operand n, Operand m, Operand d)
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{
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// V = (Rd ^ Rn) & ~(Rn ^ Rm) < 0
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Operand vOut = context.BitwiseExclusiveOr(d, n);
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vOut = context.BitwiseAnd(vOut, context.BitwiseNot(context.BitwiseExclusiveOr(n, m)));
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vOut = context.ICompareLess(vOut, Const(vOut.Type, 0));
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SetFlag(context, PState.VFlag, vOut);
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}
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public static void EmitSbcsCCheck(ArmEmitterContext context, Operand n, Operand m)
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{
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// C = (Rn == Rm && CIn) || Rn > Rm
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Operand cIn = GetFlag(PState.CFlag);
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Operand cOut = context.BitwiseAnd(context.ICompareEqual(n, m), cIn);
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cOut = context.BitwiseOr(cOut, context.ICompareGreaterUI(n, m));
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SetFlag(context, PState.CFlag, cOut);
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}
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public static void EmitSubsCCheck(ArmEmitterContext context, Operand n, Operand m)
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{
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// C = Rn >= Rm
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SetFlag(context, PState.CFlag, context.ICompareGreaterOrEqualUI(n, m));
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}
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public static void EmitSubsVCheck(ArmEmitterContext context, Operand n, Operand m, Operand d)
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{
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// V = (Rd ^ Rn) & (Rn ^ Rm) < 0
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Operand vOut = context.BitwiseExclusiveOr(d, n);
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vOut = context.BitwiseAnd(vOut, context.BitwiseExclusiveOr(n, m));
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vOut = context.ICompareLess(vOut, Const(vOut.Type, 0));
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SetFlag(context, PState.VFlag, vOut);
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}
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public static Operand EmitReverseBits32Op(ArmEmitterContext context, Operand op)
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{
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Debug.Assert(op.Type == OperandType.I32);
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Operand val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(op, Const(0xaaaaaaaau)), Const(1)),
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context.ShiftLeft(context.BitwiseAnd(op, Const(0x55555555u)), Const(1)));
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val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xccccccccu)), Const(2)),
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context.ShiftLeft(context.BitwiseAnd(val, Const(0x33333333u)), Const(2)));
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val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xf0f0f0f0u)), Const(4)),
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context.ShiftLeft(context.BitwiseAnd(val, Const(0x0f0f0f0fu)), Const(4)));
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val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xff00ff00u)), Const(8)),
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context.ShiftLeft(context.BitwiseAnd(val, Const(0x00ff00ffu)), Const(8)));
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return context.BitwiseOr(context.ShiftRightUI(val, Const(16)), context.ShiftLeft(val, Const(16)));
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}
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public static Operand EmitReverseBytes16_64Op(ArmEmitterContext context, Operand op)
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{
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Debug.Assert(op.Type == OperandType.I64);
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return context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(op, Const(0xff00ff00ff00ff00ul)), Const(8)),
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context.ShiftLeft(context.BitwiseAnd(op, Const(0x00ff00ff00ff00fful)), Const(8)));
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}
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public static Operand EmitReverseBytes16_32Op(ArmEmitterContext context, Operand op)
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{
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Debug.Assert(op.Type == OperandType.I32);
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Operand val = EmitReverseBytes16_64Op(context, context.ZeroExtend32(OperandType.I64, op));
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return context.ConvertI64ToI32(val);
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}
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private static void EmitAluWritePc(ArmEmitterContext context, Operand value)
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{
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Debug.Assert(value.Type == OperandType.I32);
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if (IsThumb(context.CurrOp))
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{
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context.StoreToContext();
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bool isReturn = IsA32Return(context);
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Operand addr = context.BitwiseOr(value, Const(1));
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InstEmitFlowHelper.EmitVirtualJump(context, addr, isReturn);
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}
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else
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{
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EmitBxWritePc(context, value);
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}
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}
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public static void EmitGenericAluStoreA32(ArmEmitterContext context, int rd, bool setFlags, Operand value)
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{
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Debug.Assert(value.Type == OperandType.I32);
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if (rd == RegisterAlias.Aarch32Pc && setFlags)
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{
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if (setFlags)
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{
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// TODO: Load SPSR etc.
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EmitBxWritePc(context, value);
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}
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else
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{
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EmitAluWritePc(context, value);
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}
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}
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else
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{
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SetIntA32(context, rd, value);
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}
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}
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public static Operand GetAluN(ArmEmitterContext context)
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{
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if (context.CurrOp is IOpCodeAlu op)
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{
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if (op.DataOp == DataOp.Logical || op is IOpCodeAluRs)
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{
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return GetIntOrZR(context, op.Rn);
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}
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else
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{
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return GetIntOrSP(context, op.Rn);
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}
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}
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else if (context.CurrOp is IOpCode32Alu op32)
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{
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return GetIntA32(context, op32.Rn);
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}
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else
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{
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throw InvalidOpCodeType(context.CurrOp);
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}
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}
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public static Operand GetAluM(ArmEmitterContext context, bool setCarry = true)
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{
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switch (context.CurrOp)
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{
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// ARM32.
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case OpCode32AluImm op:
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{
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if (op.SetFlags && op.IsRotated)
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{
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SetFlag(context, PState.CFlag, Const((uint)op.Immediate >> 31));
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}
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return Const(op.Immediate);
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}
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case OpCode32AluImm16 op: return Const(op.Immediate);
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case OpCode32AluRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
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case OpCode32AluRsReg op: return GetMShiftedByReg(context, op, setCarry);
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case OpCodeT16AluImm8 op: return Const(op.Immediate);
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case IOpCode32AluReg op: return GetIntA32(context, op.Rm);
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// ARM64.
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case IOpCodeAluImm op:
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{
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if (op.GetOperandType() == OperandType.I32)
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{
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return Const((int)op.Immediate);
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}
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else
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{
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return Const(op.Immediate);
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}
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}
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case IOpCodeAluRs op:
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{
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Operand value = GetIntOrZR(context, op.Rm);
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switch (op.ShiftType)
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{
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case ShiftType.Lsl: value = context.ShiftLeft (value, Const(op.Shift)); break;
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case ShiftType.Lsr: value = context.ShiftRightUI(value, Const(op.Shift)); break;
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case ShiftType.Asr: value = context.ShiftRightSI(value, Const(op.Shift)); break;
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case ShiftType.Ror: value = context.RotateRight (value, Const(op.Shift)); break;
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}
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return value;
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}
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case IOpCodeAluRx op:
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{
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Operand value = GetExtendedM(context, op.Rm, op.IntType);
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value = context.ShiftLeft(value, Const(op.Shift));
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return value;
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}
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default: throw InvalidOpCodeType(context.CurrOp);
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}
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}
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private static Exception InvalidOpCodeType(OpCode opCode)
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{
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return new InvalidOperationException($"Invalid OpCode type \"{opCode?.GetType().Name ?? "null"}\".");
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}
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// ARM32 helpers.
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public static Operand GetMShiftedByImmediate(ArmEmitterContext context, OpCode32AluRsImm op, bool setCarry)
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{
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Operand m = GetIntA32(context, op.Rm);
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int shift = op.Immediate;
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if (shift == 0)
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{
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switch (op.ShiftType)
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{
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case ShiftType.Lsr: shift = 32; break;
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case ShiftType.Asr: shift = 32; break;
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case ShiftType.Ror: shift = 1; break;
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}
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}
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if (shift != 0)
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{
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setCarry &= op.SetFlags;
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switch (op.ShiftType)
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{
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case ShiftType.Lsl: m = GetLslC(context, m, setCarry, shift); break;
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case ShiftType.Lsr: m = GetLsrC(context, m, setCarry, shift); break;
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case ShiftType.Asr: m = GetAsrC(context, m, setCarry, shift); break;
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case ShiftType.Ror:
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if (op.Immediate != 0)
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{
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m = GetRorC(context, m, setCarry, shift);
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}
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else
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{
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m = GetRrxC(context, m, setCarry);
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}
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break;
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}
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}
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return m;
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}
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public static int DecodeImmShift(ShiftType shiftType, int shift)
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{
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if (shift == 0)
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{
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switch (shiftType)
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{
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case ShiftType.Lsr: shift = 32; break;
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case ShiftType.Asr: shift = 32; break;
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case ShiftType.Ror: shift = 1; break;
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}
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}
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return shift;
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}
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public static Operand GetMShiftedByReg(ArmEmitterContext context, OpCode32AluRsReg op, bool setCarry)
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{
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Operand m = GetIntA32(context, op.Rm);
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Operand s = context.ZeroExtend8(OperandType.I32, GetIntA32(context, op.Rs));
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Operand shiftIsZero = context.ICompareEqual(s, Const(0));
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Operand zeroResult = m;
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Operand shiftResult = m;
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setCarry &= op.SetFlags;
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switch (op.ShiftType)
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{
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case ShiftType.Lsl: shiftResult = EmitLslC(context, m, setCarry, s, shiftIsZero); break;
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case ShiftType.Lsr: shiftResult = EmitLsrC(context, m, setCarry, s, shiftIsZero); break;
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case ShiftType.Asr: shiftResult = EmitAsrC(context, m, setCarry, s, shiftIsZero); break;
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case ShiftType.Ror: shiftResult = EmitRorC(context, m, setCarry, s, shiftIsZero); break;
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}
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return context.ConditionalSelect(shiftIsZero, zeroResult, shiftResult);
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}
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public static void EmitIfHelper(ArmEmitterContext context, Operand boolValue, Action action, bool expected = true)
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{
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Debug.Assert(boolValue.Type == OperandType.I32);
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Operand endLabel = Label();
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if (expected)
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{
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context.BranchIfFalse(endLabel, boolValue);
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}
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else
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{
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context.BranchIfTrue(endLabel, boolValue);
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}
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action();
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context.MarkLabel(endLabel);
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}
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public static Operand EmitLslC(ArmEmitterContext context, Operand m, bool setCarry, Operand shift, Operand shiftIsZero)
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{
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Debug.Assert(m.Type == OperandType.I32 && shift.Type == OperandType.I32 && shiftIsZero.Type == OperandType.I32);
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Operand shiftLarge = context.ICompareGreaterOrEqual(shift, Const(32));
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Operand result = context.ShiftLeft(m, shift);
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if (setCarry)
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{
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EmitIfHelper(context, shiftIsZero, () =>
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{
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Operand cOut = context.ShiftRightUI(m, context.Subtract(Const(32), shift));
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cOut = context.BitwiseAnd(cOut, Const(1));
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cOut = context.ConditionalSelect(context.ICompareGreater(shift, Const(32)), Const(0), cOut);
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SetFlag(context, PState.CFlag, cOut);
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}, false);
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}
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return context.ConditionalSelect(shiftLarge, Const(0), result);
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}
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public static Operand GetLslC(ArmEmitterContext context, Operand m, bool setCarry, int shift)
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{
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Debug.Assert(m.Type == OperandType.I32);
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if ((uint)shift > 32)
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{
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return GetShiftByMoreThan32(context, setCarry);
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}
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else if (shift == 32)
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{
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if (setCarry)
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{
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SetCarryMLsb(context, m);
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}
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return Const(0);
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}
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else
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{
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if (setCarry)
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{
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Operand cOut = context.ShiftRightUI(m, Const(32 - shift));
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cOut = context.BitwiseAnd(cOut, Const(1));
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SetFlag(context, PState.CFlag, cOut);
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}
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return context.ShiftLeft(m, Const(shift));
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}
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}
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public static Operand EmitLsrC(ArmEmitterContext context, Operand m, bool setCarry, Operand shift, Operand shiftIsZero)
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{
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Debug.Assert(m.Type == OperandType.I32 && shift.Type == OperandType.I32 && shiftIsZero.Type == OperandType.I32);
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Operand shiftLarge = context.ICompareGreaterOrEqual(shift, Const(32));
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Operand result = context.ShiftRightUI(m, shift);
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if (setCarry)
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{
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EmitIfHelper(context, shiftIsZero, () =>
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{
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Operand cOut = context.ShiftRightUI(m, context.Subtract(shift, Const(1)));
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cOut = context.BitwiseAnd(cOut, Const(1));
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cOut = context.ConditionalSelect(context.ICompareGreater(shift, Const(32)), Const(0), cOut);
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SetFlag(context, PState.CFlag, cOut);
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}, false);
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}
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return context.ConditionalSelect(shiftLarge, Const(0), result);
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}
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public static Operand GetLsrC(ArmEmitterContext context, Operand m, bool setCarry, int shift)
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{
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Debug.Assert(m.Type == OperandType.I32);
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if ((uint)shift > 32)
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{
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return GetShiftByMoreThan32(context, setCarry);
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}
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else if (shift == 32)
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{
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if (setCarry)
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{
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SetCarryMMsb(context, m);
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}
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return Const(0);
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}
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else
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{
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if (setCarry)
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{
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SetCarryMShrOut(context, m, shift);
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}
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return context.ShiftRightUI(m, Const(shift));
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}
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}
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private static Operand GetShiftByMoreThan32(ArmEmitterContext context, bool setCarry)
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{
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if (setCarry)
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{
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SetFlag(context, PState.CFlag, Const(0));
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}
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return Const(0);
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}
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public static Operand EmitAsrC(ArmEmitterContext context, Operand m, bool setCarry, Operand shift, Operand shiftIsZero)
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{
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Debug.Assert(m.Type == OperandType.I32 && shift.Type == OperandType.I32 && shiftIsZero.Type == OperandType.I32);
|
|
|
|
Operand l32Result;
|
|
Operand ge32Result;
|
|
|
|
Operand less32 = context.ICompareLess(shift, Const(32));
|
|
|
|
ge32Result = context.ShiftRightSI(m, Const(31));
|
|
|
|
if (setCarry)
|
|
{
|
|
EmitIfHelper(context, context.BitwiseOr(less32, shiftIsZero), () =>
|
|
{
|
|
SetCarryMLsb(context, ge32Result);
|
|
}, false);
|
|
}
|
|
|
|
l32Result = context.ShiftRightSI(m, shift);
|
|
if (setCarry)
|
|
{
|
|
EmitIfHelper(context, context.BitwiseAnd(less32, context.BitwiseNot(shiftIsZero)), () =>
|
|
{
|
|
Operand cOut = context.ShiftRightUI(m, context.Subtract(shift, Const(1)));
|
|
|
|
cOut = context.BitwiseAnd(cOut, Const(1));
|
|
|
|
SetFlag(context, PState.CFlag, cOut);
|
|
});
|
|
}
|
|
|
|
return context.ConditionalSelect(less32, l32Result, ge32Result);
|
|
}
|
|
|
|
public static Operand GetAsrC(ArmEmitterContext context, Operand m, bool setCarry, int shift)
|
|
{
|
|
Debug.Assert(m.Type == OperandType.I32);
|
|
|
|
if ((uint)shift >= 32)
|
|
{
|
|
m = context.ShiftRightSI(m, Const(31));
|
|
|
|
if (setCarry)
|
|
{
|
|
SetCarryMLsb(context, m);
|
|
}
|
|
|
|
return m;
|
|
}
|
|
else
|
|
{
|
|
if (setCarry)
|
|
{
|
|
SetCarryMShrOut(context, m, shift);
|
|
}
|
|
|
|
return context.ShiftRightSI(m, Const(shift));
|
|
}
|
|
}
|
|
|
|
public static Operand EmitRorC(ArmEmitterContext context, Operand m, bool setCarry, Operand shift, Operand shiftIsZero)
|
|
{
|
|
Debug.Assert(m.Type == OperandType.I32 && shift.Type == OperandType.I32 && shiftIsZero.Type == OperandType.I32);
|
|
|
|
shift = context.BitwiseAnd(shift, Const(0x1f));
|
|
m = context.RotateRight(m, shift);
|
|
|
|
if (setCarry)
|
|
{
|
|
EmitIfHelper(context, shiftIsZero, () =>
|
|
{
|
|
SetCarryMMsb(context, m);
|
|
}, false);
|
|
}
|
|
|
|
return m;
|
|
}
|
|
|
|
public static Operand GetRorC(ArmEmitterContext context, Operand m, bool setCarry, int shift)
|
|
{
|
|
Debug.Assert(m.Type == OperandType.I32);
|
|
|
|
shift &= 0x1f;
|
|
|
|
m = context.RotateRight(m, Const(shift));
|
|
|
|
if (setCarry)
|
|
{
|
|
SetCarryMMsb(context, m);
|
|
}
|
|
|
|
return m;
|
|
}
|
|
|
|
public static Operand GetRrxC(ArmEmitterContext context, Operand m, bool setCarry)
|
|
{
|
|
Debug.Assert(m.Type == OperandType.I32);
|
|
|
|
// Rotate right by 1 with carry.
|
|
Operand cIn = context.Copy(GetFlag(PState.CFlag));
|
|
|
|
if (setCarry)
|
|
{
|
|
SetCarryMLsb(context, m);
|
|
}
|
|
|
|
m = context.ShiftRightUI(m, Const(1));
|
|
|
|
m = context.BitwiseOr(m, context.ShiftLeft(cIn, Const(31)));
|
|
|
|
return m;
|
|
}
|
|
|
|
private static void SetCarryMLsb(ArmEmitterContext context, Operand m)
|
|
{
|
|
Debug.Assert(m.Type == OperandType.I32);
|
|
|
|
SetFlag(context, PState.CFlag, context.BitwiseAnd(m, Const(1)));
|
|
}
|
|
|
|
private static void SetCarryMMsb(ArmEmitterContext context, Operand m)
|
|
{
|
|
Debug.Assert(m.Type == OperandType.I32);
|
|
|
|
SetFlag(context, PState.CFlag, context.ShiftRightUI(m, Const(31)));
|
|
}
|
|
|
|
private static void SetCarryMShrOut(ArmEmitterContext context, Operand m, int shift)
|
|
{
|
|
Debug.Assert(m.Type == OperandType.I32);
|
|
|
|
Operand cOut = context.ShiftRightUI(m, Const(shift - 1));
|
|
|
|
cOut = context.BitwiseAnd(cOut, Const(1));
|
|
|
|
SetFlag(context, PState.CFlag, cOut);
|
|
}
|
|
}
|
|
}
|