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* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
382 lines
13 KiB
C#
382 lines
13 KiB
C#
using ARMeilleure.Common;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System.Collections.Generic;
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using System.Diagnostics;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.CodeGen.RegisterAllocators
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{
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class HybridAllocator : IRegisterAllocator
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{
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private const int RegistersCount = 16;
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private const int MaxIROperands = 4;
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private struct BlockInfo
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{
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public bool HasCall { get; }
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public int IntFixedRegisters { get; }
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public int VecFixedRegisters { get; }
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public BlockInfo(bool hasCall, int intFixedRegisters, int vecFixedRegisters)
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{
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HasCall = hasCall;
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IntFixedRegisters = intFixedRegisters;
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VecFixedRegisters = vecFixedRegisters;
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}
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}
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private class LocalInfo
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{
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public int Uses { get; set; }
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public int UseCount { get; set; }
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public bool PreAllocated { get; set; }
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public int Register { get; set; }
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public int SpillOffset { get; set; }
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public int Sequence { get; set; }
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public Operand Temp { get; set; }
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public OperandType Type { get; }
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private int _first;
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private int _last;
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public bool IsBlockLocal => _first == _last;
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public LocalInfo(OperandType type, int uses)
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{
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Uses = uses;
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Type = type;
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_first = -1;
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_last = -1;
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}
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public void SetBlockIndex(int blkIndex)
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{
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if (_first == -1 || blkIndex < _first)
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{
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_first = blkIndex;
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}
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if (_last == -1 || blkIndex > _last)
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{
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_last = blkIndex;
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}
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}
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}
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public AllocationResult RunPass(
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ControlFlowGraph cfg,
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StackAllocator stackAlloc,
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RegisterMasks regMasks)
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{
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int intUsedRegisters = 0;
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int vecUsedRegisters = 0;
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int intFreeRegisters = regMasks.IntAvailableRegisters;
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int vecFreeRegisters = regMasks.VecAvailableRegisters;
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BlockInfo[] blockInfo = new BlockInfo[cfg.Blocks.Count];
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List<LocalInfo> locInfo = new List<LocalInfo>();
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for (int index = cfg.PostOrderBlocks.Length - 1; index >= 0; index--)
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{
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BasicBlock block = cfg.PostOrderBlocks[index];
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int intFixedRegisters = 0;
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int vecFixedRegisters = 0;
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bool hasCall = false;
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foreach (Node node in block.Operations)
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{
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if (node is Operation operation && operation.Instruction == Instruction.Call)
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{
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hasCall = true;
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}
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for (int srcIndex = 0; srcIndex < node.SourcesCount; srcIndex++)
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{
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Operand source = node.GetSource(srcIndex);
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if (source.Kind == OperandKind.LocalVariable)
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{
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locInfo[source.AsInt32() - 1].SetBlockIndex(block.Index);
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}
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}
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for (int dstIndex = 0; dstIndex < node.DestinationsCount; dstIndex++)
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{
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Operand dest = node.GetDestination(dstIndex);
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if (dest.Kind == OperandKind.LocalVariable)
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{
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LocalInfo info;
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if (dest.Value != 0)
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{
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info = locInfo[dest.AsInt32() - 1];
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}
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else
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{
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dest.NumberLocal(locInfo.Count + 1);
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info = new LocalInfo(dest.Type, UsesCount(dest));
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locInfo.Add(info);
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}
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info.SetBlockIndex(block.Index);
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}
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else if (dest.Kind == OperandKind.Register)
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{
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if (dest.Type.IsInteger())
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{
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intFixedRegisters |= 1 << dest.GetRegister().Index;
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}
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else
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{
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vecFixedRegisters |= 1 << dest.GetRegister().Index;
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}
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}
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}
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}
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blockInfo[block.Index] = new BlockInfo(hasCall, intFixedRegisters, vecFixedRegisters);
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}
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int sequence = 0;
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for (int index = cfg.PostOrderBlocks.Length - 1; index >= 0; index--)
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{
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BasicBlock block = cfg.PostOrderBlocks[index];
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BlockInfo blkInfo = blockInfo[block.Index];
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int intLocalFreeRegisters = intFreeRegisters & ~blkInfo.IntFixedRegisters;
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int vecLocalFreeRegisters = vecFreeRegisters & ~blkInfo.VecFixedRegisters;
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int intCallerSavedRegisters = blkInfo.HasCall ? regMasks.IntCallerSavedRegisters : 0;
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int vecCallerSavedRegisters = blkInfo.HasCall ? regMasks.VecCallerSavedRegisters : 0;
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int intSpillTempRegisters = SelectSpillTemps(
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intCallerSavedRegisters & ~blkInfo.IntFixedRegisters,
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intLocalFreeRegisters);
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int vecSpillTempRegisters = SelectSpillTemps(
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vecCallerSavedRegisters & ~blkInfo.VecFixedRegisters,
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vecLocalFreeRegisters);
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intLocalFreeRegisters &= ~(intSpillTempRegisters | intCallerSavedRegisters);
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vecLocalFreeRegisters &= ~(vecSpillTempRegisters | vecCallerSavedRegisters);
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for (LinkedListNode<Node> llNode = block.Operations.First; llNode != null; llNode = llNode.Next)
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{
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Node node = llNode.Value;
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int intLocalUse = 0;
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int vecLocalUse = 0;
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for (int srcIndex = 0; srcIndex < node.SourcesCount; srcIndex++)
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{
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Operand source = node.GetSource(srcIndex);
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if (source.Kind != OperandKind.LocalVariable)
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{
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continue;
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}
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LocalInfo info = locInfo[source.AsInt32() - 1];
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info.UseCount++;
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Debug.Assert(info.UseCount <= info.Uses);
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if (info.Register != -1)
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{
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node.SetSource(srcIndex, Register(info.Register, source.Type.ToRegisterType(), source.Type));
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if (info.UseCount == info.Uses && !info.PreAllocated)
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{
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if (source.Type.IsInteger())
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{
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intLocalFreeRegisters |= 1 << info.Register;
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}
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else
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{
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vecLocalFreeRegisters |= 1 << info.Register;
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}
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}
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}
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else
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{
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Operand temp = info.Temp;
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if (temp == null || info.Sequence != sequence)
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{
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temp = source.Type.IsInteger()
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? GetSpillTemp(source, intSpillTempRegisters, ref intLocalUse)
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: GetSpillTemp(source, vecSpillTempRegisters, ref vecLocalUse);
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info.Sequence = sequence;
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info.Temp = temp;
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}
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node.SetSource(srcIndex, temp);
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Operation fillOp = new Operation(Instruction.Fill, temp, Const(info.SpillOffset));
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block.Operations.AddBefore(llNode, fillOp);
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}
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}
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int intLocalAsg = 0;
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int vecLocalAsg = 0;
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for (int dstIndex = 0; dstIndex < node.DestinationsCount; dstIndex++)
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{
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Operand dest = node.GetDestination(dstIndex);
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if (dest.Kind != OperandKind.LocalVariable)
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{
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continue;
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}
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LocalInfo info = locInfo[dest.AsInt32() - 1];
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if (info.UseCount == 0 && !info.PreAllocated)
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{
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int mask = dest.Type.IsInteger()
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? intLocalFreeRegisters
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: vecLocalFreeRegisters;
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if (info.IsBlockLocal && mask != 0)
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{
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int selectedReg = BitUtils.LowestBitSet(mask);
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info.Register = selectedReg;
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if (dest.Type.IsInteger())
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{
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intLocalFreeRegisters &= ~(1 << selectedReg);
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intUsedRegisters |= 1 << selectedReg;
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}
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else
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{
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vecLocalFreeRegisters &= ~(1 << selectedReg);
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vecUsedRegisters |= 1 << selectedReg;
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}
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}
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else
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{
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info.Register = -1;
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info.SpillOffset = stackAlloc.Allocate(dest.Type.GetSizeInBytes());
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}
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}
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info.UseCount++;
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Debug.Assert(info.UseCount <= info.Uses);
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if (info.Register != -1)
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{
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node.SetDestination(dstIndex, Register(info.Register, dest.Type.ToRegisterType(), dest.Type));
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}
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else
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{
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Operand temp = info.Temp;
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if (temp == null || info.Sequence != sequence)
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{
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temp = dest.Type.IsInteger()
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? GetSpillTemp(dest, intSpillTempRegisters, ref intLocalAsg)
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: GetSpillTemp(dest, vecSpillTempRegisters, ref vecLocalAsg);
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info.Sequence = sequence;
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info.Temp = temp;
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}
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node.SetDestination(dstIndex, temp);
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Operation spillOp = new Operation(Instruction.Spill, null, Const(info.SpillOffset), temp);
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llNode = block.Operations.AddAfter(llNode, spillOp);
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}
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}
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sequence++;
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intUsedRegisters |= intLocalAsg | intLocalUse;
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vecUsedRegisters |= vecLocalAsg | vecLocalUse;
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}
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}
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return new AllocationResult(intUsedRegisters, vecUsedRegisters, stackAlloc.TotalSize);
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}
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private static int SelectSpillTemps(int mask0, int mask1)
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{
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int selection = 0;
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int count = 0;
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while (count < MaxIROperands && mask0 != 0)
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{
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int mask = mask0 & -mask0;
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selection |= mask;
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mask0 &= ~mask;
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count++;
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}
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while (count < MaxIROperands && mask1 != 0)
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{
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int mask = mask1 & -mask1;
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selection |= mask;
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mask1 &= ~mask;
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count++;
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}
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Debug.Assert(count == MaxIROperands, "No enough registers for spill temps.");
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return selection;
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}
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private static Operand GetSpillTemp(Operand local, int freeMask, ref int useMask)
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{
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int selectedReg = BitUtils.LowestBitSet(freeMask & ~useMask);
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useMask |= 1 << selectedReg;
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return Register(selectedReg, local.Type.ToRegisterType(), local.Type);
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}
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private static int UsesCount(Operand local)
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{
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return local.Assignments.Count + local.Uses.Count;
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}
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private static IEnumerable<BasicBlock> Successors(BasicBlock block)
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{
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if (block.Next != null)
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{
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yield return block.Next;
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}
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if (block.Branch != null)
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{
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yield return block.Branch;
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}
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}
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}
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} |