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Ryujinx/ChocolArm64
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LDj3SNuD ffbfbb5549 Add FCVT <Hd>, <Sn> and FCVT <Sd>, <Hn> Inst.; add Tests. (#692) 
* Update OpCodeTable.cs

* Update InstEmitSimdCvt.cs

* Update CpuTestSimd.cs

* Address PR feedback.
2019-05-30 19:51:39 -03:00
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Instructions Add FCVT <Hd>, <Sn> and FCVT <Sd>, <Hn> Inst.; add Tests. (#692) 2019-05-30 19:51:39 -03:00
IntermediateRepresentation
Memory
State
Translation
ChocolArm64.csproj
CpuThread.cs
OpCodeTable.cs Add FCVT <Hd>, <Sn> and FCVT <Sd>, <Hn> Inst.; add Tests. (#692) 2019-05-30 19:51:39 -03:00
Optimizations.cs