mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-07-14 01:31:45 +02:00
a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
448 lines
16 KiB
C#
448 lines
16 KiB
C#
#define SimdRegElemF
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using ARMeilleure.State;
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using NUnit.Framework;
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using System.Collections.Generic;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdRegElemF")]
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public sealed class CpuTestSimdRegElemF : CpuTest
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{
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#if SimdRegElemF
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#region "ValueSource (Types)"
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private static IEnumerable<ulong> _1S_F_()
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{
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yield return 0x00000000FF7FFFFFul; // -Max Normal (float.MinValue)
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yield return 0x0000000080800000ul; // -Min Normal
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yield return 0x00000000807FFFFFul; // -Max Subnormal
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yield return 0x0000000080000001ul; // -Min Subnormal (-float.Epsilon)
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yield return 0x000000007F7FFFFFul; // +Max Normal (float.MaxValue)
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yield return 0x0000000000800000ul; // +Min Normal
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yield return 0x00000000007FFFFFul; // +Max Subnormal
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yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon)
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if (!NoZeros)
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{
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yield return 0x0000000080000000ul; // -Zero
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yield return 0x0000000000000000ul; // +Zero
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}
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if (!NoInfs)
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{
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yield return 0x00000000FF800000ul; // -Infinity
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yield return 0x000000007F800000ul; // +Infinity
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}
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if (!NoNaNs)
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{
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yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
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yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload)
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yield return 0x000000007FC00000ul; // +QNaN (all zeros payload) (-float.NaN) (DefaultNaN)
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yield return 0x000000007FBFFFFFul; // +SNaN (all ones payload)
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}
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for (int cnt = 1; cnt <= RndCnt; cnt++)
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{
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ulong grbg = TestContext.CurrentContext.Random.NextUInt();
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ulong rnd1 = GenNormalS();
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ulong rnd2 = GenSubnormalS();
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yield return (grbg << 32) | rnd1;
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yield return (grbg << 32) | rnd2;
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}
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}
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private static IEnumerable<ulong> _2S_F_()
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{
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yield return 0xFF7FFFFFFF7FFFFFul; // -Max Normal (float.MinValue)
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yield return 0x8080000080800000ul; // -Min Normal
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yield return 0x807FFFFF807FFFFFul; // -Max Subnormal
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yield return 0x8000000180000001ul; // -Min Subnormal (-float.Epsilon)
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yield return 0x7F7FFFFF7F7FFFFFul; // +Max Normal (float.MaxValue)
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yield return 0x0080000000800000ul; // +Min Normal
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yield return 0x007FFFFF007FFFFFul; // +Max Subnormal
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yield return 0x0000000100000001ul; // +Min Subnormal (float.Epsilon)
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if (!NoZeros)
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{
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yield return 0x8000000080000000ul; // -Zero
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yield return 0x0000000000000000ul; // +Zero
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}
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if (!NoInfs)
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{
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yield return 0xFF800000FF800000ul; // -Infinity
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yield return 0x7F8000007F800000ul; // +Infinity
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}
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if (!NoNaNs)
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{
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yield return 0xFFC00000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
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yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones payload)
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yield return 0x7FC000007FC00000ul; // +QNaN (all zeros payload) (-float.NaN) (DefaultNaN)
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yield return 0x7FBFFFFF7FBFFFFFul; // +SNaN (all ones payload)
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}
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for (int cnt = 1; cnt <= RndCnt; cnt++)
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{
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ulong rnd1 = GenNormalS();
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ulong rnd2 = GenSubnormalS();
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yield return (rnd1 << 32) | rnd1;
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yield return (rnd2 << 32) | rnd2;
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}
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}
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private static IEnumerable<ulong> _1D_F_()
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{
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yield return 0xFFEFFFFFFFFFFFFFul; // -Max Normal (double.MinValue)
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yield return 0x8010000000000000ul; // -Min Normal
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yield return 0x800FFFFFFFFFFFFFul; // -Max Subnormal
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yield return 0x8000000000000001ul; // -Min Subnormal (-double.Epsilon)
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yield return 0x7FEFFFFFFFFFFFFFul; // +Max Normal (double.MaxValue)
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yield return 0x0010000000000000ul; // +Min Normal
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yield return 0x000FFFFFFFFFFFFFul; // +Max Subnormal
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yield return 0x0000000000000001ul; // +Min Subnormal (double.Epsilon)
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if (!NoZeros)
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{
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yield return 0x8000000000000000ul; // -Zero
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yield return 0x0000000000000000ul; // +Zero
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}
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if (!NoInfs)
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{
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yield return 0xFFF0000000000000ul; // -Infinity
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yield return 0x7FF0000000000000ul; // +Infinity
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}
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if (!NoNaNs)
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{
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yield return 0xFFF8000000000000ul; // -QNaN (all zeros payload) (double.NaN)
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yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones payload)
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yield return 0x7FF8000000000000ul; // +QNaN (all zeros payload) (-double.NaN) (DefaultNaN)
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yield return 0x7FF7FFFFFFFFFFFFul; // +SNaN (all ones payload)
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}
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for (int cnt = 1; cnt <= RndCnt; cnt++)
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{
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ulong rnd1 = GenNormalD();
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ulong rnd2 = GenSubnormalD();
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yield return rnd1;
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yield return rnd2;
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}
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}
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _F_Mla_Mls_Se_S_()
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{
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return new uint[]
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{
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0x5F821020u, // FMLA S0, S1, V2.S[0]
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0x5F825020u // FMLS S0, S1, V2.S[0]
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};
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}
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private static uint[] _F_Mla_Mls_Se_D_()
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{
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return new uint[]
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{
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0x5FC21020u, // FMLA D0, D1, V2.D[0]
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0x5FC25020u // FMLS D0, D1, V2.D[0]
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};
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}
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private static uint[] _F_Mla_Mls_Ve_2S_4S_()
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{
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return new uint[]
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{
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0x0F801000u, // FMLA V0.2S, V0.2S, V0.S[0]
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0x0F805000u // FMLS V0.2S, V0.2S, V0.S[0]
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};
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}
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private static uint[] _F_Mla_Mls_Ve_2D_()
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{
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return new uint[]
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{
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0x4FC01000u, // FMLA V0.2D, V0.2D, V0.D[0]
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0x4FC05000u // FMLS V0.2D, V0.2D, V0.D[0]
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};
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}
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private static uint[] _F_Mul_Mulx_Se_S_()
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{
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return new uint[]
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{
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0x5F829020u, // FMUL S0, S1, V2.S[0]
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0x7F829020u // FMULX S0, S1, V2.S[0]
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};
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}
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private static uint[] _F_Mul_Mulx_Se_D_()
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{
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return new uint[]
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{
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0x5FC29020u, // FMUL D0, D1, V2.D[0]
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0x7FC29020u // FMULX D0, D1, V2.D[0]
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};
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}
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private static uint[] _F_Mul_Mulx_Ve_2S_4S_()
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{
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return new uint[]
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{
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0x0F809000u, // FMUL V0.2S, V0.2S, V0.S[0]
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0x2F809000u // FMULX V0.2S, V0.2S, V0.S[0]
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};
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}
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private static uint[] _F_Mul_Mulx_Ve_2D_()
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{
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return new uint[]
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{
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0x4FC09000u, // FMUL V0.2D, V0.2D, V0.D[0]
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0x6FC09000u // FMULX V0.2D, V0.2D, V0.D[0]
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};
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}
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#endregion
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private const int RndCnt = 2;
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private static readonly bool NoZeros = false;
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private static readonly bool NoInfs = false;
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private static readonly bool NoNaNs = false;
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[Test, Pairwise] [Explicit] // Fused.
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public void F_Mla_Mls_Se_S([ValueSource("_F_Mla_Mls_Se_S_")] uint opcodes,
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[ValueSource("_1S_F_")] ulong z,
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[ValueSource("_1S_F_")] ulong a,
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[ValueSource("_2S_F_")] ulong b,
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[Values(0u, 1u, 2u, 3u)] uint index)
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{
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uint h = (index >> 1) & 1;
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uint l = index & 1;
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opcodes |= (l << 21) | (h << 11);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0(a);
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V128 v2 = MakeVectorE0E1(b, b * h);
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int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
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int fpcr = rnd & (1 << (int)Fpcr.Fz);
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fpcr |= rnd & (1 << (int)Fpcr.Dn);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
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CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsS);
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}
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[Test, Pairwise] [Explicit] // Fused.
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public void F_Mla_Mls_Se_D([ValueSource("_F_Mla_Mls_Se_D_")] uint opcodes,
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[ValueSource("_1D_F_")] ulong z,
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[ValueSource("_1D_F_")] ulong a,
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[ValueSource("_1D_F_")] ulong b,
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[Values(0u, 1u)] uint index)
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{
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uint h = index & 1;
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opcodes |= h << 11;
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0(a);
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V128 v2 = MakeVectorE0E1(b, b * h);
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int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
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int fpcr = rnd & (1 << (int)Fpcr.Fz);
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fpcr |= rnd & (1 << (int)Fpcr.Dn);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
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CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsD);
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}
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[Test, Pairwise] [Explicit] // Fused.
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public void F_Mla_Mls_Ve_2S_4S([ValueSource("_F_Mla_Mls_Ve_2S_4S_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(2u, 0u)] uint rm,
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[ValueSource("_2S_F_")] ulong z,
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[ValueSource("_2S_F_")] ulong a,
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[ValueSource("_2S_F_")] ulong b,
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[Values(0u, 1u, 2u, 3u)] uint index,
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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{
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uint h = (index >> 1) & 1;
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uint l = index & 1;
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (l << 21) | (h << 11);
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opcodes |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a * q);
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V128 v2 = MakeVectorE0E1(b, b * h);
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int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
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int fpcr = rnd & (1 << (int)Fpcr.Fz);
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fpcr |= rnd & (1 << (int)Fpcr.Dn);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
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CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsS);
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}
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[Test, Pairwise] [Explicit] // Fused.
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public void F_Mla_Mls_Ve_2D([ValueSource("_F_Mla_Mls_Ve_2D_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(2u, 0u)] uint rm,
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[ValueSource("_1D_F_")] ulong z,
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[ValueSource("_1D_F_")] ulong a,
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[ValueSource("_1D_F_")] ulong b,
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[Values(0u, 1u)] uint index)
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{
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uint h = index & 1;
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= h << 11;
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a);
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V128 v2 = MakeVectorE0E1(b, b * h);
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int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
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int fpcr = rnd & (1 << (int)Fpcr.Fz);
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fpcr |= rnd & (1 << (int)Fpcr.Dn);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
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CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsD);
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}
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[Test, Pairwise] [Explicit]
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public void F_Mul_Mulx_Se_S([ValueSource("_F_Mul_Mulx_Se_S_")] uint opcodes,
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[ValueSource("_1S_F_")] ulong a,
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[ValueSource("_2S_F_")] ulong b,
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[Values(0u, 1u, 2u, 3u)] uint index)
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{
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uint h = (index >> 1) & 1;
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uint l = index & 1;
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opcodes |= (l << 21) | (h << 11);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0(a);
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V128 v2 = MakeVectorE0E1(b, b * h);
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int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
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int fpcr = rnd & (1 << (int)Fpcr.Fz);
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fpcr |= rnd & (1 << (int)Fpcr.Dn);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
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CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
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}
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[Test, Pairwise] [Explicit]
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public void F_Mul_Mulx_Se_D([ValueSource("_F_Mul_Mulx_Se_D_")] uint opcodes,
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[ValueSource("_1D_F_")] ulong a,
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[ValueSource("_1D_F_")] ulong b,
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[Values(0u, 1u)] uint index)
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{
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uint h = index & 1;
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opcodes |= h << 11;
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE1(z);
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V128 v1 = MakeVectorE0(a);
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V128 v2 = MakeVectorE0E1(b, b * h);
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int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
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int fpcr = rnd & (1 << (int)Fpcr.Fz);
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fpcr |= rnd & (1 << (int)Fpcr.Dn);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
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CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
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}
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[Test, Pairwise] [Explicit]
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public void F_Mul_Mulx_Ve_2S_4S([ValueSource("_F_Mul_Mulx_Ve_2S_4S_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(2u, 0u)] uint rm,
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[ValueSource("_2S_F_")] ulong z,
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[ValueSource("_2S_F_")] ulong a,
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[ValueSource("_2S_F_")] ulong b,
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[Values(0u, 1u, 2u, 3u)] uint index,
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
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{
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uint h = (index >> 1) & 1;
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uint l = index & 1;
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|
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (l << 21) | (h << 11);
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opcodes |= ((q & 1) << 30);
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|
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a * q);
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V128 v2 = MakeVectorE0E1(b, b * h);
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|
|
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int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
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|
|
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int fpcr = rnd & (1 << (int)Fpcr.Fz);
|
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fpcr |= rnd & (1 << (int)Fpcr.Dn);
|
|
|
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
|
|
|
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CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
|
|
}
|
|
|
|
[Test, Pairwise] [Explicit]
|
|
public void F_Mul_Mulx_Ve_2D([ValueSource("_F_Mul_Mulx_Ve_2D_")] uint opcodes,
|
|
[Values(0u)] uint rd,
|
|
[Values(1u, 0u)] uint rn,
|
|
[Values(2u, 0u)] uint rm,
|
|
[ValueSource("_1D_F_")] ulong z,
|
|
[ValueSource("_1D_F_")] ulong a,
|
|
[ValueSource("_1D_F_")] ulong b,
|
|
[Values(0u, 1u)] uint index)
|
|
{
|
|
uint h = index & 1;
|
|
|
|
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
opcodes |= h << 11;
|
|
|
|
V128 v0 = MakeVectorE0E1(z, z);
|
|
V128 v1 = MakeVectorE0E1(a, a);
|
|
V128 v2 = MakeVectorE0E1(b, b * h);
|
|
|
|
int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
int fpcr = rnd & (1 << (int)Fpcr.Fz);
|
|
fpcr |= rnd & (1 << (int)Fpcr.Dn);
|
|
|
|
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
|
|
|
|
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
|
|
}
|
|
#endif
|
|
}
|
|
}
|