mirror of
https://github.com/Ryujinx/Ryujinx.git
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b1b6f294f2
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure 😩
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
93 lines
4.2 KiB
C#
93 lines
4.2 KiB
C#
using ARMeilleure.State;
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using System;
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namespace ARMeilleure.Instructions
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{
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delegate double _F64_F64(double a1);
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delegate double _F64_F64_Bool(double a1, bool a2);
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delegate double _F64_F64_F64(double a1, double a2);
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delegate double _F64_F64_F64_Bool(double a1, double a2, bool a3);
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delegate double _F64_F64_F64_F64(double a1, double a2, double a3);
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delegate double _F64_F64_F64_F64_Bool(double a1, double a2, double a3, bool a4);
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delegate double _F64_F64_MidpointRounding(double a1, MidpointRounding a2);
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delegate float _F32_F32(float a1);
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delegate float _F32_F32_Bool(float a1, bool a2);
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delegate float _F32_F32_F32(float a1, float a2);
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delegate float _F32_F32_F32_Bool(float a1, float a2, bool a3);
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delegate float _F32_F32_F32_F32(float a1, float a2, float a3);
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delegate float _F32_F32_F32_F32_Bool(float a1, float a2, float a3, bool a4);
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delegate float _F32_F32_MidpointRounding(float a1, MidpointRounding a2);
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delegate float _F32_U16(ushort a1);
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delegate int _S32_F32(float a1);
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delegate int _S32_F32_F32_Bool(float a1, float a2, bool a3);
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delegate int _S32_F64(double a1);
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delegate int _S32_F64_F64_Bool(double a1, double a2, bool a3);
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delegate int _S32_U64_U16(ulong a1, ushort a2);
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delegate int _S32_U64_U32(ulong a1, uint a2);
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delegate int _S32_U64_U64(ulong a1, ulong a2);
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delegate int _S32_U64_U8(ulong a1, byte a2);
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delegate int _S32_U64_V128(ulong a1, V128 a2);
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delegate long _S64_F32(float a1);
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delegate long _S64_F64(double a1);
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delegate long _S64_S64(long a1);
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delegate long _S64_S64_S32(long a1, int a2);
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delegate long _S64_S64_S64(long a1, long a2);
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delegate long _S64_S64_S64_Bool_S32(long a1, long a2, bool a3, int a4);
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delegate long _S64_S64_S64_S32(long a1, long a2, int a3);
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delegate long _S64_U64_S32(ulong a1, int a2);
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delegate long _S64_U64_S64(ulong a1, long a2);
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delegate ushort _U16_F32(float a1);
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delegate ushort _U16_U64(ulong a1);
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delegate uint _U32();
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delegate uint _U32_F32(float a1);
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delegate uint _U32_F64(double a1);
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delegate uint _U32_U32(uint a1);
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delegate uint _U32_U32_U16(uint a1, ushort a2);
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delegate uint _U32_U32_U32(uint a1, uint a2);
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delegate uint _U32_U32_U64(uint a1, ulong a2);
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delegate uint _U32_U32_U8(uint a1, byte a2);
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delegate uint _U32_U64(ulong a1);
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delegate ulong _U64();
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delegate ulong _U64_F32(float a1);
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delegate ulong _U64_F64(double a1);
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delegate ulong _U64_S64_S32(long a1, int a2);
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delegate ulong _U64_S64_U64(long a1, ulong a2);
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delegate ulong _U64_U64(ulong a1);
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delegate ulong _U64_U64_S32(ulong a1, int a2);
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delegate ulong _U64_U64_S64_S32(ulong a1, long a2, int a3);
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delegate ulong _U64_U64_U64(ulong a1, ulong a2);
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delegate ulong _U64_U64_U64_Bool_S32(ulong a1, ulong a2, bool a3, int a4);
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delegate byte _U8_U64(ulong a1);
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delegate V128 _V128_U64(ulong a1);
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delegate V128 _V128_V128(V128 a1);
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delegate V128 _V128_V128_S32_V128(V128 a1, int a2, V128 a3);
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delegate V128 _V128_V128_S32_V128_V128(V128 a1, int a2, V128 a3, V128 a4);
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delegate V128 _V128_V128_S32_V128_V128_V128(V128 a1, int a2, V128 a3, V128 a4, V128 a5);
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delegate V128 _V128_V128_S32_V128_V128_V128_V128(V128 a1, int a2, V128 a3, V128 a4, V128 a5, V128 a6);
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delegate V128 _V128_V128_U32_V128(V128 a1, uint a2, V128 a3);
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delegate V128 _V128_V128_V128(V128 a1, V128 a2);
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delegate V128 _V128_V128_V128_S32_V128(V128 a1, V128 a2, int a3, V128 a4);
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delegate V128 _V128_V128_V128_S32_V128_V128(V128 a1, V128 a2, int a3, V128 a4, V128 a5);
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delegate V128 _V128_V128_V128_S32_V128_V128_V128(V128 a1, V128 a2, int a3, V128 a4, V128 a5, V128 a6);
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delegate V128 _V128_V128_V128_S32_V128_V128_V128_V128(V128 a1, V128 a2, int a3, V128 a4, V128 a5, V128 a6, V128 a7);
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delegate V128 _V128_V128_V128_V128(V128 a1, V128 a2, V128 a3);
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delegate void _Void();
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delegate void _Void_U32(uint a1);
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delegate void _Void_U64(ulong a1);
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delegate void _Void_U64_S32(ulong a1, int a2);
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delegate void _Void_U64_U16(ulong a1, ushort a2);
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delegate void _Void_U64_U32(ulong a1, uint a2);
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delegate void _Void_U64_U64(ulong a1, ulong a2);
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delegate void _Void_U64_U8(ulong a1, byte a2);
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delegate void _Void_U64_V128(ulong a1, V128 a2);
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}
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