mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-30 01:04:13 +01:00
56 lines
1.6 KiB
ArmAsm
56 lines
1.6 KiB
ArmAsm
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# See LICENSE for license details.
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#*****************************************************************************
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# andi.S
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#-----------------------------------------------------------------------------
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#
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# Test andi instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Logical tests
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#-------------------------------------------------------------
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TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f );
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TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 );
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TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f );
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TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 );
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#-------------------------------------------------------------
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# Source/Destination tests
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#-------------------------------------------------------------
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TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 );
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#-------------------------------------------------------------
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# Bypassing tests
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#-------------------------------------------------------------
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TEST_IMM_DEST_BYPASS( 7, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
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TEST_IMM_DEST_BYPASS( 8, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
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TEST_IMM_DEST_BYPASS( 9, 2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f );
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TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
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TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
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TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f );
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TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 );
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TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f );
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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