mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-11 14:14:14 +01:00
93 lines
2.4 KiB
Systemverilog
93 lines
2.4 KiB
Systemverilog
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module mcu_spi (
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input clk,
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input reset,
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output logic frame_start,
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output logic data_ready,
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output logic [7:0] rx_data,
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input [7:0] tx_data,
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input mcu_clk,
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input mcu_cs,
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input mcu_mosi,
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output logic mcu_miso
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);
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logic [2:0] mcu_clk_ff;
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logic [2:0] mcu_cs_ff;
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always_ff @(posedge clk) begin
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mcu_clk_ff <= {mcu_clk_ff[1:0], mcu_clk};
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mcu_cs_ff <= {mcu_cs_ff[1:0], mcu_cs};
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end
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logic mcu_clk_falling;
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logic mcu_clk_rising;
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logic mcu_cs_falling;
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logic mcu_cs_rising;
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always_comb begin
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mcu_clk_falling = mcu_clk_ff[2] && !mcu_clk_ff[1];
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mcu_clk_rising = !mcu_clk_ff[2] && mcu_clk_ff[1];
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mcu_cs_falling = mcu_cs_ff[2] && !mcu_cs_ff[1];
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mcu_cs_rising = !mcu_cs_ff[2] && mcu_cs_ff[1];
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end
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logic mcu_dq_in;
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logic mcu_dq_out;
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logic mcu_miso_out;
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assign mcu_miso = mcu_cs_ff[1] ? 1'bZ : mcu_miso_out;
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always_ff @(posedge clk) begin
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mcu_dq_in <= mcu_mosi;
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mcu_miso_out <= mcu_dq_out;
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end
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logic [7:0] spi_tx_shift;
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assign mcu_dq_out = spi_tx_shift[7];
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logic spi_enabled;
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logic [2:0] spi_bit_counter;
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always_ff @(posedge clk) begin
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frame_start <= 1'b0;
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data_ready <= 1'b0;
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if (reset) begin
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spi_enabled <= 1'b0;
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spi_bit_counter <= 3'd0;
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end else begin
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if (mcu_cs_falling) begin
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spi_enabled <= 1'b1;
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spi_bit_counter <= 3'd0;
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frame_start <= 1'b1;
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end
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if (mcu_cs_rising) begin
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spi_enabled <= 1'b0;
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end
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if (spi_enabled) begin
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if (mcu_clk_rising) begin
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if (spi_bit_counter == 3'd0) begin
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spi_tx_shift <= tx_data;
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end else begin
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spi_tx_shift <= {spi_tx_shift[6:0], 1'b0};
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end
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end
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if (mcu_clk_falling) begin
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spi_bit_counter <= spi_bit_counter + 1'd1;
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rx_data <= {rx_data[6:0], mcu_dq_in};
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if (spi_bit_counter == 3'd7) begin
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data_ready <= 1'b1;
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end
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end
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end
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end
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end
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endmodule
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