mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-05 19:34:14 +01:00
128 lines
2.9 KiB
Systemverilog
128 lines
2.9 KiB
Systemverilog
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module vendor (
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input clk,
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input reset,
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vendor_scb.vendor vendor_scb
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);
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logic start;
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logic busy;
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logic [1:0] length;
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logic [5:0] delay;
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logic request;
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logic write;
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logic ack;
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logic [7:0] address;
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logic [7:0] rdata;
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logic [7:0] wdata;
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logic [23:0] wdata_buffer;
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logic ufm_irq;
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always_comb begin
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start = vendor_scb.control_valid && vendor_scb.control_wdata[0] && !busy;
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vendor_scb.control_rdata = {
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16'd0,
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address,
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4'b0000,
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length,
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write,
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busy
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};
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end
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always_ff @(posedge clk) begin
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if (reset) begin
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busy <= 1'b0;
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end else begin
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if (start) begin
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busy <= 1'b1;
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end
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if (length == 2'd0 && ack) begin
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busy <= 1'b0;
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end
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end
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end
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always_ff @(posedge clk) begin
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if (start) begin
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length <= vendor_scb.control_wdata[3:2];
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end
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if (ack && length > 2'd0) begin
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length <= length - 1'd1;
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end
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end
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always_ff @(posedge clk) begin
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if (reset) begin
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delay <= 6'd0;
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end else begin
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if (start && vendor_scb.control_wdata[4]) begin
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delay <= 6'd35;
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end
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if (delay > 6'd0) begin
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delay <= delay - 1'd1;
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end
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end
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end
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always_ff @(posedge clk) begin
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if (reset) begin
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request <= 1'b0;
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end else begin
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if (start) begin
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request <= 1'b1;
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end
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if (busy && !request && delay == 6'd0) begin
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request <= 1'b1;
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end
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if (ack) begin
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request <= 1'b0;
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end
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end
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end
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always_ff @(posedge clk) begin
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if (start) begin
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write <= vendor_scb.control_wdata[1];
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end
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end
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always_ff @(posedge clk) begin
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if (start) begin
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address <= vendor_scb.control_wdata[15:8];
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end
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end
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always_ff @(posedge clk) begin
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if (ack) begin
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vendor_scb.data_rdata <= {vendor_scb.data_rdata[23:0], rdata};
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end
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end
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always_ff @(posedge clk) begin
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if (start) begin
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{wdata, wdata_buffer} <= vendor_scb.data_wdata;
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end
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if (ack) begin
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{wdata, wdata_buffer} <= {wdata_buffer, 8'h00};
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end
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end
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efb_lattice_generated efb_lattice_generated_inst (
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.wb_clk_i(clk),
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.wb_rst_i(reset),
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.wb_cyc_i(request),
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.wb_stb_i(request),
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.wb_we_i(write),
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.wb_adr_i(address),
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.wb_dat_i(wdata),
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.wb_dat_o(rdata),
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.wb_ack_o(ack),
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.wbc_ufm_irq(ufm_irq)
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);
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endmodule
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