SummerCart64/fw/rtl/SummerCart64.sv

77 lines
1.7 KiB
Systemverilog
Raw Normal View History

2021-08-01 15:32:48 +02:00
module SummerCart64 (
input i_clk,
2021-08-12 21:07:47 +02:00
output o_usb_clk,
output o_usb_cs,
input i_usb_miso,
inout [3:0] io_usb_miosi,
2021-08-15 21:49:02 +02:00
// output o_ftdi_clk,
// output o_ftdi_si,
// input i_ftdi_so,
// input i_ftdi_cts,
2021-08-01 15:32:48 +02:00
input i_n64_reset,
input i_n64_nmi,
2021-08-12 21:07:47 +02:00
output o_n64_irq,
2021-08-01 15:32:48 +02:00
input i_n64_pi_alel,
input i_n64_pi_aleh,
input i_n64_pi_read,
input i_n64_pi_write,
inout [15:0] io_n64_pi_ad,
input i_n64_si_clk,
inout io_n64_si_dq,
output o_sdram_clk,
output o_sdram_cs,
output o_sdram_ras,
output o_sdram_cas,
output o_sdram_we,
output [1:0] o_sdram_ba,
output [12:0] o_sdram_a,
inout [15:0] io_sdram_dq,
output o_sd_clk,
inout io_sd_cmd,
inout [3:0] io_sd_dat,
2021-08-15 21:49:02 +02:00
// output o_flash_clk,
// output o_flash_cs,
// inout io_flash_dq[3:0],
2021-08-05 19:50:29 +02:00
inout io_rtc_scl,
2021-08-01 15:32:48 +02:00
inout io_rtc_sda,
output o_led,
2021-08-12 21:07:47 +02:00
inout [0:0] io_pmod
2021-08-01 15:32:48 +02:00
);
2021-08-05 19:50:29 +02:00
if_system system_if (.in_clk(i_clk));
system system_inst (.system_if(system_if));
2021-08-01 15:32:48 +02:00
2021-08-12 21:07:47 +02:00
wire [7:0] gpio_o;
wire [7:0] gpio_i;
wire [7:0] gpio_oe;
assign o_led = gpio_oe[0] ? gpio_o[0] : 1'bZ;
assign o_n64_irq = gpio_oe[1] ? gpio_o[1] : 1'bZ;
2021-08-15 21:49:02 +02:00
assign gpio_i = {io_pmod[0], 3'b000, i_n64_nmi, i_n64_reset, o_n64_irq, o_led};
2021-08-01 15:32:48 +02:00
2021-08-12 21:07:47 +02:00
cpu_soc cpu_soc_inst (
2021-08-15 21:49:02 +02:00
.system_if(system_if),
2021-08-12 21:07:47 +02:00
.gpio_o(gpio_o),
.gpio_i(gpio_i),
.gpio_oe(gpio_oe),
.usb_clk(o_usb_clk),
.usb_cs(o_usb_cs),
.usb_miso(i_usb_miso),
.usb_miosi(io_usb_miosi),
2021-08-15 21:49:02 +02:00
.i2c_scl(io_rtc_scl),
.i2c_sda(io_rtc_sda)
2021-08-12 21:07:47 +02:00
);
2021-08-01 15:32:48 +02:00
endmodule