mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
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63 lines
1.7 KiB
Coq
63 lines
1.7 KiB
Coq
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module sd_dma (
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input i_clk,
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input i_reset,
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input i_fifo_flush,
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input i_fifo_push,
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output o_fifo_full,
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output o_fifo_empty,
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input [31:0] i_fifo_data,
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output reg o_request,
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output reg o_write,
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input i_busy,
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output reg [31:0] o_data
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);
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reg [31:0] r_dma_fifo_mem [0:127];
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reg [6:0] r_dma_fifo_wrptr;
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reg [6:0] r_dma_fifo_rdptr;
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assign o_fifo_full = (r_dma_fifo_wrptr + 1'd1) == r_dma_fifo_rdptr;
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assign o_fifo_empty = r_dma_fifo_wrptr == r_dma_fifo_rdptr;
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wire [31:0] w_rddata = r_dma_fifo_mem[r_dma_fifo_rdptr];
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wire w_request_successful = o_request && !i_busy;
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always @(posedge i_clk) begin
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if (i_reset || i_fifo_flush) begin
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r_dma_fifo_wrptr <= 7'd0;
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end else begin
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if (i_fifo_push) begin
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r_dma_fifo_wrptr <= r_dma_fifo_wrptr + 1'd1;
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r_dma_fifo_mem[r_dma_fifo_wrptr] <= i_fifo_data;
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end
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end
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end
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always @(posedge i_clk) begin
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if (i_reset || i_fifo_flush) begin
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o_request <= 1'b0;
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o_write <= 1'b1;
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r_dma_fifo_rdptr <= 7'd0;
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end else begin
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if (!o_request && !o_fifo_empty) begin
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o_request <= 1'b1;
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o_data <= w_rddata;
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r_dma_fifo_rdptr <= r_dma_fifo_rdptr + 1'd1;
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end
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if (w_request_successful) begin
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if (o_fifo_empty) begin
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o_request <= 1'b0;
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end else begin
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r_dma_fifo_rdptr <= r_dma_fifo_rdptr + 1'd1;
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o_data <= w_rddata;
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end
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end
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end
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end
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endmodule
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