2021-08-27 21:43:30 +02:00
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#include "sys.h"
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#include "process.h"
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static const uint8_t cmd_token[3] = { 'C', 'M', 'D' };
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static const uint8_t cmp_token[3] = { 'C', 'M', 'P' };
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static const uint8_t err_token[3] = { 'E', 'R', 'R' };
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static uint8_t save_type = 0;
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static uint16_t cic_type = 0xFFFF;
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static uint8_t tv_type = 0xFF;
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2021-08-28 17:57:48 +02:00
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static uint32_t *save_pointer = (uint32_t *) (SDRAM_BASE + DEFAULT_SAVE_OFFSET);
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2021-08-27 21:43:30 +02:00
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void process_usb (void);
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void process_cfg (void);
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void process_dd (void);
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void process_si (void);
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void process_uart (void);
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2021-08-28 04:15:24 +02:00
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void process_rtc (void);
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2021-08-28 17:57:48 +02:00
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void process_flashram (void);
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2021-08-27 21:43:30 +02:00
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void cfg_set_save_type (uint8_t type);
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void cfg_update_config (uint32_t *args);
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2021-08-28 17:57:48 +02:00
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// void print (const char *text);
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// void print_02hex (unsigned char number);
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2021-08-27 21:43:30 +02:00
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void process (void) {
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while (1) {
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process_usb();
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process_cfg();
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process_dd();
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process_si();
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process_uart();
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2021-08-28 04:15:24 +02:00
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process_rtc();
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2021-08-28 17:57:48 +02:00
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process_flashram();
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2021-08-27 21:43:30 +02:00
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}
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}
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void process_usb (void) {
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static int state = 0;
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static uint8_t current_byte = 0;
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static uint8_t cmd;
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static uint32_t args[2];
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static uint8_t is_error;
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static uint8_t dma_started;
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uint8_t data;
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switch (state) {
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case 0: {
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if (USB->SCR & USB_SCR_RXNE) {
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data = USB->DR;
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if (current_byte == 3) {
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state = 1;
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current_byte = 0;
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cmd = data;
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args[0] = 0;
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args[1] = 0;
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is_error = 0;
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dma_started = 0;
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break;
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}
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if (data != cmd_token[current_byte]) {
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current_byte = 0;
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break;
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}
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current_byte += 1;
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}
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break;
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}
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case 1: {
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if (USB->SCR & USB_SCR_RXNE) {
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data = USB->DR;
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uint32_t *p = args + (current_byte >= 4 ? 1 : 0);
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*p = (*p << 8) | data;
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current_byte += 1;
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if (current_byte == 8) {
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state = 2;
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current_byte = 0;
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break;
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}
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}
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break;
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}
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case 2: {
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if (cmd == 'R' || cmd == 'W') {
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if (!dma_started) {
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if (!(DMA->SCR & DMA_SCR_BUSY)) {
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DMA->MADDR = args[0];
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DMA->ID_LEN = args[1];
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DMA->SCR = (cmd == 'W' ? DMA_SCR_DIR : 0) | DMA_SCR_START;
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dma_started = 1;
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}
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} else {
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if (!(DMA->SCR & DMA_SCR_BUSY)) {
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state = 3;
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}
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}
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} else if (cmd == 'C') {
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cfg_update_config(args);
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state = 3;
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} else {
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state = 3;
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is_error = 1;
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}
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break;
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}
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case 3: {
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if (USB->SCR & USB_SCR_TXE) {
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const uint8_t *p = is_error ? err_token : cmp_token;
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USB->DR = (current_byte < 3) ? p[current_byte] : cmd;
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current_byte += 1;
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if (current_byte == 4) {
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state = 0;
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current_byte = 0;
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}
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}
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break;
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}
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default: {
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state = 0;
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break;
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}
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}
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}
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void process_cfg (void) {
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static uint8_t state = 0;
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static uint8_t cmd;
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static uint32_t args[3];
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switch (state) {
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case 0: {
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if (CFG->SCR & CFG_SCR_CPU_BUSY) {
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state = 1;
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cmd = CFG->CMD;
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args[0] = CFG->DATA[0];
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args[1] = CFG->DATA[1];
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}
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break;
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}
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case 1: {
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if (cmd == 'C') {
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cfg_update_config(args);
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CFG->DATA[0] = (save_type << 8) | (CFG->SCR & 0x07);
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CFG->DATA[1] = (tv_type << 16) | cic_type;
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state = 2;
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} else {
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CFG->DATA[0] = 0xFFFFFFFF;
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CFG->DATA[1] = 0xFFFFFFFF;
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state = 2;
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}
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break;
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}
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case 2: {
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CFG->SCR &= ~(CFG_SCR_CPU_BUSY);
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state = 0;
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break;
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}
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default: {
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state = 0;
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break;
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}
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}
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}
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void process_dd (void) {
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}
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void process_si (void) {
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}
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void process_uart (void) {
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if (UART->SCR & UART_SCR_RXNE) {
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uint8_t data = UART->DR;
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if (data == '/') {
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while (!(UART->SCR & UART_SCR_TXE));
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UART->DR = '>';
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void (*bootloader) (void) = (void *) &BOOTLOADER;
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bootloader();
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}
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}
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}
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2021-08-28 04:15:24 +02:00
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void process_rtc (void) {
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}
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2021-08-28 17:57:48 +02:00
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void process_flashram (void) {
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uint32_t scr = FLASHRAM->SCR;
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volatile uint32_t *offset_pointer = save_pointer;
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size_t length;
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if (scr & FLASHRAM_OPERATION_PENDING) {
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if (scr & FLASHRAM_WRITE_OR_ERASE) {
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if (scr & FLASHRAM_SECTOR_OR_ALL) {
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length = 128 * 1024;
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} else {
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offset_pointer += 32 * (scr >> FLASHRAM_SECTOR_BIT);
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length = 16 * 1024;
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}
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for (size_t i = 0; i < (length / 4); i++) {
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offset_pointer[i] = 0xFFFFFFFF;
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}
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} else {
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offset_pointer += 32 * (scr >> FLASHRAM_SECTOR_BIT);
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for (size_t i = 0; i < 32; i++) {
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offset_pointer[i] &= FLASHRAM->BUFFER[i];
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}
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}
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FLASHRAM->SCR = FLASHRAM_OPERATION_DONE;
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}
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}
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2021-08-28 02:37:02 +02:00
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void cfg_update_config (uint32_t *args) {
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switch (args[0]) {
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2021-08-27 21:43:30 +02:00
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case 0: {
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2021-08-28 02:37:02 +02:00
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if (args[1]) {
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CFG->SCR |= CFG_SCR_SDRAM_SWITCH;
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} else {
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CFG->SCR &= ~CFG_SCR_SDRAM_SWITCH;
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}
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2021-08-27 21:43:30 +02:00
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break;
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}
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case 1: {
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2021-08-28 02:37:02 +02:00
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if (args[1]) {
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CFG->SCR |= CFG_SCR_SDRAM_WRITABLE;
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} else {
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CFG->SCR &= ~CFG_SCR_SDRAM_WRITABLE;
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}
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2021-08-27 21:43:30 +02:00
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break;
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}
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case 2: {
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2021-08-28 02:37:02 +02:00
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if (args[1]) {
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CFG->SCR |= CFG_SCR_DD_EN;
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} else {
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CFG->SCR &= ~CFG_SCR_DD_EN;
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}
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2021-08-27 21:43:30 +02:00
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break;
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}
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case 3: {
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2021-08-28 02:37:02 +02:00
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cfg_set_save_type(args[1] & 0xFF);
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2021-08-27 21:43:30 +02:00
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break;
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}
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case 4: {
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2021-08-28 02:37:02 +02:00
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cic_type = args[1] & 0xFFFF;
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2021-08-27 21:43:30 +02:00
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break;
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}
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case 5: {
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2021-08-28 02:37:02 +02:00
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tv_type = args[1] & 0xFF;
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2021-08-27 21:43:30 +02:00
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break;
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}
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}
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}
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2021-08-28 02:37:02 +02:00
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void cfg_set_save_type (uint8_t type) {
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CFG->SCR &= ~(CFG_SCR_FLASHRAM_EN | CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN);
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2021-08-28 17:57:48 +02:00
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uint32_t save_offset = 0;
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2021-08-28 02:37:02 +02:00
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switch (type) {
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2021-08-27 21:43:30 +02:00
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case 0: {
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break;
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}
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case 1: {
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2021-08-28 17:57:48 +02:00
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save_offset = SDRAM_SIZE - 512;
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2021-08-27 21:43:30 +02:00
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break;
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}
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case 2: {
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2021-08-28 17:57:48 +02:00
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save_offset = SDRAM_SIZE - 2048;
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2021-08-27 21:43:30 +02:00
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break;
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}
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case 3: {
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2021-08-28 17:57:48 +02:00
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save_offset = SDRAM_SIZE - (32 * 1024);
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2021-08-28 02:37:02 +02:00
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CFG->SCR |= CFG_SCR_SRAM_EN;
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2021-08-27 21:43:30 +02:00
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break;
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}
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case 4: {
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2021-08-28 17:57:48 +02:00
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save_offset = SDRAM_SIZE - (256 * 1024);
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2021-08-28 02:37:02 +02:00
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CFG->SCR |= CFG_SCR_FLASHRAM_EN;
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2021-08-27 21:43:30 +02:00
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break;
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}
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case 5: {
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2021-08-28 17:57:48 +02:00
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save_offset = SDRAM_SIZE - (3 * 32 * 1024);
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2021-08-28 02:37:02 +02:00
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CFG->SCR |= CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN;
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2021-08-27 21:43:30 +02:00
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break;
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}
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2021-08-28 02:37:02 +02:00
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case 6: {
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2021-08-28 17:57:48 +02:00
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save_offset = 0x01608000;
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2021-08-28 02:37:02 +02:00
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CFG->SCR |= CFG_SCR_FLASHRAM_EN;
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break;
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}
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default: {
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return;
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}
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2021-08-27 21:43:30 +02:00
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}
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2021-08-28 02:37:02 +02:00
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2021-08-28 17:57:48 +02:00
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save_pointer = (uint32_t *) (SDRAM_BASE + save_offset);
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2021-08-28 02:37:02 +02:00
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save_type = type;
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2021-08-28 17:57:48 +02:00
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CFG->SAVE_OFFSET = save_offset;
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2021-08-27 21:43:30 +02:00
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}
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2021-08-28 04:15:24 +02:00
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// void print (const char *text) {
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// while (*text != '\0') {
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// while (!(UART->SCR & UART_SCR_TXE));
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// UART->DR = *text++;
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// }
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// }
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// const char hex_char_map[16] = {
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// '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'
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// };
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// void print_02hex (unsigned char number) {
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// char buffer[3];
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// buffer[0] = hex_char_map[number >> 4];
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// buffer[1] = hex_char_map[number & 0x0F];
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// buffer[2] = '\0';
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// print(buffer);
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// }
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