mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-02 01:54:14 +01:00
110 lines
3.2 KiB
Coq
110 lines
3.2 KiB
Coq
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module testbench(input clk, mem_ready_0, mem_ready_1);
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// set this to 1 to test generation of counter examples
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localparam ENABLE_COUNTERS = 0;
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reg resetn = 0;
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always @(posedge clk) resetn <= 1;
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(* keep *) wire trap_0, trace_valid_0, mem_valid_0, mem_instr_0;
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(* keep *) wire [3:0] mem_wstrb_0;
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(* keep *) wire [31:0] mem_addr_0, mem_wdata_0, mem_rdata_0;
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(* keep *) wire [35:0] trace_data_0;
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(* keep *) wire trap_1, trace_valid_1, mem_valid_1, mem_instr_1;
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(* keep *) wire [3:0] mem_wstrb_1;
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(* keep *) wire [31:0] mem_addr_1, mem_wdata_1, mem_rdata_1;
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(* keep *) wire [35:0] trace_data_1;
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reg [31:0] mem_0 [0:2**30-1];
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reg [31:0] mem_1 [0:2**30-1];
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assign mem_rdata_0 = mem_0[mem_addr_0 >> 2];
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assign mem_rdata_1 = mem_1[mem_addr_1 >> 2];
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always @(posedge clk) begin
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if (resetn && mem_valid_0 && mem_ready_0) begin
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if (mem_wstrb_0[3]) mem_0[mem_addr_0 >> 2][31:24] <= mem_wdata_0[31:24];
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if (mem_wstrb_0[2]) mem_0[mem_addr_0 >> 2][23:16] <= mem_wdata_0[23:16];
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if (mem_wstrb_0[1]) mem_0[mem_addr_0 >> 2][15: 8] <= mem_wdata_0[15: 8];
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if (mem_wstrb_0[0]) mem_0[mem_addr_0 >> 2][ 7: 0] <= mem_wdata_0[ 7: 0];
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end
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if (resetn && mem_valid_1 && mem_ready_1) begin
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if (mem_wstrb_1[3]) mem_1[mem_addr_1 >> 2][31:24] <= mem_wdata_1[31:24];
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if (mem_wstrb_1[2]) mem_1[mem_addr_1 >> 2][23:16] <= mem_wdata_1[23:16];
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if (mem_wstrb_1[1]) mem_1[mem_addr_1 >> 2][15: 8] <= mem_wdata_1[15: 8];
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if (mem_wstrb_1[0]) mem_1[mem_addr_1 >> 2][ 7: 0] <= mem_wdata_1[ 7: 0];
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end
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end
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(* keep *) reg [7:0] trace_balance;
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reg [7:0] trace_balance_q;
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always @* begin
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trace_balance = trace_balance_q;
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if (trace_valid_0) trace_balance = trace_balance + 1;
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if (trace_valid_1) trace_balance = trace_balance - 1;
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end
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always @(posedge clk) begin
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trace_balance_q <= resetn ? trace_balance : 0;
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end
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picorv32 #(
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// do not change this settings
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.ENABLE_COUNTERS(ENABLE_COUNTERS),
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.ENABLE_TRACE(1),
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// change this settings as you like
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.ENABLE_REGS_DUALPORT(1),
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.TWO_STAGE_SHIFT(1),
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.BARREL_SHIFTER(0),
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.TWO_CYCLE_COMPARE(0),
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.TWO_CYCLE_ALU(0),
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.COMPRESSED_ISA(0),
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.ENABLE_MUL(0),
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.ENABLE_DIV(0)
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) cpu_0 (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap_0 ),
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.mem_valid (mem_valid_0 ),
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.mem_instr (mem_instr_0 ),
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.mem_ready (mem_ready_0 ),
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.mem_addr (mem_addr_0 ),
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.mem_wdata (mem_wdata_0 ),
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.mem_wstrb (mem_wstrb_0 ),
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.mem_rdata (mem_rdata_0 ),
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.trace_valid (trace_valid_0),
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.trace_data (trace_data_0 )
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);
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picorv32 #(
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// do not change this settings
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.ENABLE_COUNTERS(ENABLE_COUNTERS),
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.ENABLE_TRACE(1),
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// change this settings as you like
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.ENABLE_REGS_DUALPORT(1),
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.TWO_STAGE_SHIFT(1),
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.BARREL_SHIFTER(0),
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.TWO_CYCLE_COMPARE(0),
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.TWO_CYCLE_ALU(0),
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.COMPRESSED_ISA(0),
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.ENABLE_MUL(0),
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.ENABLE_DIV(0)
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) cpu_1 (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap_1 ),
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.mem_valid (mem_valid_1 ),
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.mem_instr (mem_instr_1 ),
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.mem_ready (mem_ready_1 ),
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.mem_addr (mem_addr_1 ),
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.mem_wdata (mem_wdata_1 ),
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.mem_wstrb (mem_wstrb_1 ),
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.mem_rdata (mem_rdata_1 ),
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.trace_valid (trace_valid_1),
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.trace_data (trace_data_1 )
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);
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endmodule
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