SummerCart64/fw/rtl/system/config.sv

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Systemverilog
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interface if_config ();
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logic cpu_ready;
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logic cpu_busy;
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logic cmd_request;
logic [7:0] cmd;
logic [31:0] data [0:1];
logic [1:0] data_write;
logic [31:0] wdata;
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logic sdram_switch;
logic sdram_writable;
logic dd_enabled;
logic sram_enabled;
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logic sram_banked;
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logic flashram_enabled;
logic flashram_read_mode;
logic [25:0] dd_offset;
logic [25:0] save_offset;
modport pi (
input sdram_switch,
input sdram_writable,
input dd_enabled,
input sram_enabled,
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input sram_banked,
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input flashram_enabled,
input flashram_read_mode,
input dd_offset,
input save_offset
);
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modport flashram (
output flashram_read_mode
);
modport n64 (
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input cpu_ready,
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input cpu_busy,
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output cmd_request,
output cmd,
output data,
input data_write,
input wdata
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);
modport cpu (
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output cpu_ready,
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output cpu_busy,
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input cmd_request,
input cmd,
input data,
output data_write,
output wdata,
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output sdram_switch,
output sdram_writable,
output dd_enabled,
output sram_enabled,
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output sram_banked,
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output flashram_enabled,
output dd_offset,
output save_offset
);
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endinterface