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38 lines
733 B
Systemverilog
38 lines
733 B
Systemverilog
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interface fifo_bus ();
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logic rx_empty;
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logic rx_almost_empty;
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logic rx_read;
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logic [7:0] rx_rdata;
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logic tx_full;
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logic tx_almost_full;
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logic tx_write;
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logic [7:0] tx_wdata;
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modport controller (
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input rx_empty,
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input rx_almost_empty,
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output rx_read,
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input rx_rdata,
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input tx_full,
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input tx_almost_full,
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output tx_write,
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output tx_wdata
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);
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modport fifo (
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output rx_empty,
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output rx_almost_empty,
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input rx_read,
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output rx_rdata,
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output tx_full,
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output tx_almost_full,
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input tx_write,
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input tx_wdata
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);
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endinterface
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