mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
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91 lines
1.7 KiB
ArmAsm
91 lines
1.7 KiB
ArmAsm
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# See LICENSE for license details.
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#*****************************************************************************
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# jalr.S
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#-----------------------------------------------------------------------------
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#
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# Test jalr instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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.option norvc
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Test 2: Basic test
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#-------------------------------------------------------------
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test_2:
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li TESTNUM, 2
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li x31, 0
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la x2, target_2
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linkaddr_2:
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jalr x19, x2, 0
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nop
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nop
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j fail
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target_2:
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la x1, linkaddr_2
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addi x1, x1, 4
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bne x1, x19, fail
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#-------------------------------------------------------------
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# Test 3: Check r0 target and that r31 is not modified
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#-------------------------------------------------------------
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test_3:
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li TESTNUM, 3
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li x31, 0
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la x3, target_3
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linkaddr_3:
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jalr x0, x3, 0
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nop
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j fail
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target_3:
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bne x31, x0, fail
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#-------------------------------------------------------------
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# Bypassing tests
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#-------------------------------------------------------------
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TEST_JALR_SRC1_BYPASS( 4, 0, jalr );
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TEST_JALR_SRC1_BYPASS( 5, 1, jalr );
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TEST_JALR_SRC1_BYPASS( 6, 2, jalr );
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#-------------------------------------------------------------
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# Test delay slot instructions not executed nor bypassed
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#-------------------------------------------------------------
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TEST_CASE( 7, x1, 4, \
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li x1, 1; \
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la x2, 1f;
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jalr x19, x2, -4; \
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addi x1, x1, 1; \
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addi x1, x1, 1; \
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addi x1, x1, 1; \
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addi x1, x1, 1; \
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1: addi x1, x1, 1; \
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addi x1, x1, 1; \
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)
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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