mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-27 05:21:55 +01:00
97 lines
2.5 KiB
ArmAsm
97 lines
2.5 KiB
ArmAsm
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# See LICENSE for license details.
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#*****************************************************************************
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# sh.S
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#-----------------------------------------------------------------------------
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#
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# Test sh instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Basic tests
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#-------------------------------------------------------------
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TEST_ST_OP( 2, lh, sh, 0x000000aa, 0, tdat );
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TEST_ST_OP( 3, lh, sh, 0xffffaa00, 2, tdat );
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TEST_ST_OP( 4, lw, sh, 0xbeef0aa0, 4, tdat );
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TEST_ST_OP( 5, lh, sh, 0xffffa00a, 6, tdat );
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# Test with negative offset
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TEST_ST_OP( 6, lh, sh, 0x000000aa, -6, tdat8 );
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TEST_ST_OP( 7, lh, sh, 0xffffaa00, -4, tdat8 );
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TEST_ST_OP( 8, lh, sh, 0x00000aa0, -2, tdat8 );
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TEST_ST_OP( 9, lh, sh, 0xffffa00a, 0, tdat8 );
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# Test with a negative base
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TEST_CASE( 10, x3, 0x5678, \
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la x1, tdat9; \
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li x2, 0x12345678; \
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addi x4, x1, -32; \
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sh x2, 32(x4); \
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lh x3, 0(x1); \
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)
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# Test with unaligned base
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TEST_CASE( 11, x3, 0x3098, \
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la x1, tdat9; \
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li x2, 0x00003098; \
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addi x1, x1, -5; \
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sh x2, 7(x1); \
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la x4, tdat10; \
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lh x3, 0(x4); \
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)
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#-------------------------------------------------------------
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# Bypassing tests
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#-------------------------------------------------------------
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TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffccdd, 0, tdat );
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TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffbccd, 2, tdat );
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TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffbbcc, 4, tdat );
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TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffabbc, 6, tdat );
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TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffaabb, 8, tdat );
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TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffdaab, 10, tdat );
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TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0, tdat );
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TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2, tdat );
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TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4, tdat );
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TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat );
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TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat );
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TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat );
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li a0, 0xbeef
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la a1, tdat
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sh a0, 6(a1)
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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tdat:
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tdat1: .half 0xbeef
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tdat2: .half 0xbeef
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tdat3: .half 0xbeef
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tdat4: .half 0xbeef
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tdat5: .half 0xbeef
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tdat6: .half 0xbeef
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tdat7: .half 0xbeef
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tdat8: .half 0xbeef
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tdat9: .half 0xbeef
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tdat10: .half 0xbeef
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RVTEST_DATA_END
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