SummerCart64/fw/rtl/cpu/cpu_bus.sv

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Systemverilog
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interface if_cpu_bus ();
localparam [3:0] NUM_DEVICES = sc64::__ID_CPU_END;
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logic request;
logic ack;
logic [3:0] wmask;
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logic [31:0] address;
logic [31:0] wdata;
logic [31:0] rdata;
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logic device_ack [(NUM_DEVICES - 1):0];
logic [31:0] device_rdata [(NUM_DEVICES - 1):0];
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always_comb begin
ack = 1'b0;
rdata = 32'd0;
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for (integer i = 0; i < NUM_DEVICES; i++) begin
ack = ack | device_ack[i];
rdata = rdata | device_rdata[i];
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end
end
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modport cpu (
output request,
input ack,
output wmask,
output address,
output wdata,
input rdata
);
genvar n;
generate
for (n = 0; n < NUM_DEVICES; n++) begin : at
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logic device_request;
always_comb begin
device_request = request && address[31:28] == n[3:0];
end
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modport device (
input .request(device_request),
output .ack(device_ack[n]),
input .wmask(wmask),
input .address(address),
input .wdata(wdata),
output .rdata(device_rdata[n])
);
end
endgenerate
endinterface