SummerCart64/fw/project/lcmxo2/sc64.ldf

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<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="sc64" device="LCMXO2-7000HC-6TG144C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy">
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<Source name="../../rtl/memory/mem_bus.sv" type="Verilog" type_short="Verilog">
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<Source name="../../rtl/fifo/fifo_junction.sv" type="Verilog" type_short="Verilog">
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<Source name="../../rtl/mcu/mcu_spi.sv" type="Verilog" type_short="Verilog">
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<Source name="../../rtl/memory/memory_dma.sv" type="Verilog" type_short="Verilog">
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