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22 lines
288 B
Systemverilog
22 lines
288 B
Systemverilog
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interface sd_scb ();
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logic [1:0] clock_mode;
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logic [5:0] index;
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modport controller (
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output clock_mode,
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output index
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);
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modport clk (
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input clock_mode
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);
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modport cmd (
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input index
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);
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endinterface
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