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25 lines
533 B
Systemverilog
25 lines
533 B
Systemverilog
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rdata
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module cpu_bootloader (
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if_system.sys system_if,
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if_cpu_bus_out cpu_bus_if,
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if_cpu_bus_in cpu_bootloader_if
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);
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wire request;
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wire [31:0] rdata;
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cpu_bus_glue #(.ADDRESS(4'hF)) cpu_bus_glue_bootloader_inst (
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.*,
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.cpu_peripheral_if(cpu_bootloader_if),
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.request(request),
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.rdata(rdata)
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);
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always_comb begin
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case (cpu_bus_if.address[6:2]){rom_formatted}
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default: rdata = 32'h0000_0000;
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endcase
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end
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endmodule
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