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32 lines
581 B
Systemverilog
32 lines
581 B
Systemverilog
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interface mem_bus ();
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logic request;
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logic ack;
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logic write;
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logic [1:0] wmask;
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logic [26:0] address;
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logic [15:0] rdata;
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logic [15:0] wdata;
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modport controller (
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output request,
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input ack,
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output write,
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output wmask,
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output address,
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input rdata,
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output wdata
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);
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modport memory (
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input request,
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output ack,
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input write,
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input wmask,
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input address,
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output rdata,
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input wdata
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);
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endinterface
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