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https://github.com/Polprzewodnikowy/SummerCart64.git
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67 lines
1.4 KiB
Systemverilog
67 lines
1.4 KiB
Systemverilog
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interface n64_reg_bus ();
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logic flashram_select;
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logic dd_select;
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logic cfg_select;
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logic read;
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logic write;
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logic [16:0] address;
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logic [15:0] rdata;
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logic [15:0] wdata;
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logic [15:0] flashram_rdata;
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logic [15:0] dd_rdata;
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logic [15:0] cfg_rdata;
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modport controller (
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output flashram_select,
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output dd_select,
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output cfg_select,
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output read,
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output write,
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output address,
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input rdata,
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output wdata
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);
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always_comb begin
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rdata = 16'd0;
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if (flashram_select) begin
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rdata = flashram_rdata;
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end
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if (dd_select) begin
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rdata = dd_rdata;
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end
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if (cfg_select) begin
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rdata = cfg_rdata;
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end
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end
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modport flashram (
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input .read(read && flashram_select),
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input .write(write && flashram_select),
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input address,
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output .rdata(flashram_rdata),
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input wdata
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);
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modport dd (
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input .read(read && dd_select),
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input .write(write && dd_select),
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input address,
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output .rdata(dd_rdata),
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input wdata
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);
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modport cfg (
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input .read(read && cfg_select),
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input .write(write && cfg_select),
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input address,
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output .rdata(cfg_rdata),
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input wdata
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);
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endinterface
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