mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-05 03:14:15 +01:00
232 lines
7.3 KiB
Systemverilog
232 lines
7.3 KiB
Systemverilog
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module sd_cmd (
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input clk,
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input reset,
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sd_scb.cmd sd_scb,
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input sd_clk_rising,
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input sd_clk_falling,
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inout sd_cmd
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);
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// Input and output data sampling
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logic sd_cmd_oe;
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logic sd_cmd_out;
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logic sd_cmd_in;
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logic sd_cmd_oe_data;
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logic sd_cmd_data;
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assign sd_cmd = sd_cmd_oe ? sd_cmd_out : 1'bZ;
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always_ff @(posedge clk) begin
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sd_cmd_oe <= sd_cmd_oe_data;
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sd_cmd_out <= sd_cmd_data;
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sd_cmd_in <= sd_cmd;
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end
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// CMD state
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typedef enum bit [1:0] {
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STATE_IDLE,
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STATE_TX,
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STATE_WAIT,
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STATE_RX
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} e_state;
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e_state state;
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e_state next_state;
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always_ff @(posedge clk) begin
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if (reset) begin
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state <= STATE_IDLE;
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end else begin
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state <= next_state;
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end
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end
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assign sd_scb.cmd_busy = (state != STATE_IDLE);
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logic [7:0] counter;
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always_comb begin
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next_state = state;
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case (state)
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STATE_IDLE: begin
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if (sd_scb.cmd_start) begin
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next_state = STATE_TX;
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end
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end
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STATE_TX: begin
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if (sd_clk_falling) begin
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if (counter == 8'd48) begin
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if (sd_scb.cmd_skip_response) begin
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next_state = STATE_IDLE;
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end else begin
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next_state = STATE_WAIT;
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end
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end
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end
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end
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STATE_WAIT: begin
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if (sd_clk_rising) begin
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if (counter == 8'd64) begin
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next_state = STATE_IDLE;
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end
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if (!sd_cmd_in) begin
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next_state = STATE_RX;
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end
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end
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end
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STATE_RX: begin
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if (sd_clk_rising) begin
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if (sd_scb.cmd_long_response) begin
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if (counter == 8'd136) begin
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next_state = STATE_IDLE;
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end
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end else begin
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if (counter == 8'd48) begin
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next_state = STATE_IDLE;
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end
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end
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end
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end
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default: begin
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next_state = STATE_IDLE;
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end
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endcase
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end
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// CRC7 unit
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logic crc_reset;
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logic crc_enable;
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logic crc_data;
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logic [6:0] crc_result;
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sd_crc_7 sd_crc_7_inst (
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.clk(clk),
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.reset(crc_reset),
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.enable(crc_enable),
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.data(crc_data),
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.result(crc_result)
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);
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// Data shifting
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logic [7:0] data_shift;
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assign crc_data = (state == STATE_RX) ? data_shift[0] : data_shift[7];
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always_ff @(posedge clk) begin
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crc_reset <= 1'b0;
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crc_enable <= 1'b0;
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if (reset) begin
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sd_cmd_oe_data <= 1'b0;
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sd_cmd_data <= 1'b1;
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end else begin
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case (state)
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STATE_IDLE: begin
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if (sd_scb.cmd_start) begin
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sd_scb.cmd_error <= 1'b0;
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crc_reset <= 1'b1;
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data_shift <= {2'b01, sd_scb.cmd_index};
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counter <= 8'd0;
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end
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end
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STATE_TX: begin
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if (sd_clk_falling) begin
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sd_cmd_oe_data <= 1'b1;
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sd_cmd_data <= data_shift[7];
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counter <= counter + 1'd1;
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crc_enable <= 1'b1;
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data_shift <= {data_shift[6:0], 1'bX};
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if (counter == 8'd7) begin
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data_shift <= sd_scb.cmd_arg[31:24];
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end
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if (counter == 8'd15) begin
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data_shift <= sd_scb.cmd_arg[23:16];
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end
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if (counter == 8'd23) begin
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data_shift <= sd_scb.cmd_arg[15:8];
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end
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if (counter == 8'd31) begin
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data_shift <= sd_scb.cmd_arg[7:0];
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end
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if (counter == 8'd39) begin
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data_shift <= {crc_result, 1'b1};
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end
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if (counter == 8'd48) begin
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sd_cmd_oe_data <= 1'b0;
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counter <= 8'd0;
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end
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end
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end
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STATE_WAIT: begin
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if (sd_clk_rising) begin
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counter <= counter + 1'd1;
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if (counter == 8'd64) begin
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sd_scb.cmd_error <= 1'b1;
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end
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if (!sd_cmd_in) begin
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counter <= 8'd1;
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crc_reset <= 1'b1;
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data_shift <= 8'h00;
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end
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end
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end
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STATE_RX: begin
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if (sd_clk_rising) begin
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counter <= counter + 1'd1;
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data_shift <= {data_shift[6:0], sd_cmd_in};
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if (counter == 8'd8) begin
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if (data_shift[6:0] != (sd_scb.cmd_reserved_response ? 7'h3F : {1'b0, sd_scb.cmd_index})) begin
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sd_scb.cmd_error <= 1'b1;
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end
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end
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if (sd_scb.cmd_long_response) begin
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if (counter >= 8'd8 && counter < 8'd128) begin
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crc_enable <= 1'b1;
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end
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if (counter[2:0] == 3'd0) begin
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sd_scb.cmd_rsp <= {sd_scb.cmd_rsp[119:0], data_shift};
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end
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if (!sd_scb.cmd_ignore_crc && counter == 8'd136) begin
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if (data_shift[7:1] != crc_result) begin
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sd_scb.cmd_error <= 1'b1;
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end
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end
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end else begin
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if (counter < 8'd40) begin
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crc_enable <= 1'b1;
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end
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if (counter <= 8'd40 && counter[2:0] == 3'd0) begin
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sd_scb.cmd_rsp <= {sd_scb.cmd_rsp[119:0], data_shift};
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end
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if (!sd_scb.cmd_ignore_crc && counter == 8'd48) begin
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if (data_shift[7:1] != crc_result) begin
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sd_scb.cmd_error <= 1'b1;
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end
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end
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end
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end
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end
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endcase
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end
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end
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endmodule
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