mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-05 03:14:15 +01:00
368 lines
11 KiB
Systemverilog
368 lines
11 KiB
Systemverilog
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module sd_dat (
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input clk,
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input reset,
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sd_scb.dat sd_scb,
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fifo_bus.fifo fifo_bus,
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input sd_clk_rising,
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input sd_clk_falling,
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inout [3:0] sd_dat
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);
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// Input and output data sampling
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logic sd_dat_oe;
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logic [3:0] sd_dat_out;
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logic [3:0] sd_dat_in;
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logic sd_dat_oe_data;
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logic [3:0] sd_dat_data;
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assign sd_dat = sd_dat_oe ? sd_dat_out : 4'hZ;
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always_ff @(posedge clk) begin
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sd_dat_oe <= sd_dat_oe_data;
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sd_dat_out <= sd_dat_data;
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sd_dat_in <= sd_dat;
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end
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always_ff @(posedge clk) begin
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sd_scb.card_busy <= !sd_dat_in[0];
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end
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// FIFO
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logic rx_full;
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logic rx_write;
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logic [7:0] rx_wdata;
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logic tx_empty;
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logic tx_read;
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logic [7:0] tx_rdata;
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fifo_8kb fifo_8kb_rx_inst (
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.clk(clk),
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.reset(reset || sd_scb.dat_fifo_flush),
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.empty(fifo_bus.rx_empty),
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.read(fifo_bus.rx_read),
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.rdata(fifo_bus.rx_rdata),
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.full(rx_full),
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.write(rx_write),
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.wdata(rx_wdata),
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.count(sd_scb.rx_count)
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);
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fifo_8kb fifo_8kb_tx_inst (
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.clk(clk),
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.reset(reset || sd_scb.dat_fifo_flush),
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.empty(tx_empty),
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.read(tx_read),
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.rdata(tx_rdata),
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.full(fifo_bus.tx_full),
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.write(fifo_bus.tx_write),
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.wdata(fifo_bus.tx_wdata),
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.count(sd_scb.tx_count)
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);
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// DAT state
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typedef enum bit [2:0] {
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STATE_IDLE,
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STATE_RX_WAIT,
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STATE_RX,
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STATE_TX_WAIT,
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STATE_TX,
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STATE_TX_STATUS_WAIT,
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STATE_TX_STATUS
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} e_state;
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e_state state;
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e_state next_state;
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always_ff @(posedge clk) begin
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if (reset || sd_scb.dat_stop) begin
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state <= STATE_IDLE;
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end else begin
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state <= next_state;
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end
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end
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assign sd_scb.dat_busy = (state != STATE_IDLE);
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logic [10:0] counter;
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logic [7:0] blocks_remaining;
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always_comb begin
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next_state = state;
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case (state)
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STATE_IDLE: begin
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if (sd_scb.dat_start_read) begin
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next_state = STATE_RX_WAIT;
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end
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if (sd_scb.dat_start_write) begin
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next_state = STATE_TX_WAIT;
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end
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end
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STATE_RX_WAIT: begin
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if (sd_clk_rising) begin
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if (!sd_dat_in[0]) begin
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next_state = STATE_RX;
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end
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end
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end
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STATE_RX: begin
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if (sd_clk_rising) begin
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if (counter == 11'd1041) begin
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if (blocks_remaining == 8'd0) begin
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next_state = STATE_IDLE;
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end else begin
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next_state = STATE_RX_WAIT;
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end
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end
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end
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end
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STATE_TX_WAIT: begin
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if (sd_clk_falling) begin
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if (sd_scb.tx_count >= 11'd512) begin
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next_state = STATE_TX;
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end
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end
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end
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STATE_TX: begin
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if (sd_clk_falling) begin
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if (counter == 11'd1042) begin
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next_state = STATE_TX_STATUS_WAIT;
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end
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end
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end
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STATE_TX_STATUS_WAIT: begin
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if (sd_clk_rising) begin
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if (counter == 11'd8) begin
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next_state = STATE_IDLE;
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end else if (!sd_dat_in[0]) begin
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next_state = STATE_TX_STATUS;
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end
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end
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end
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STATE_TX_STATUS: begin
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if (sd_clk_rising) begin
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if (counter == 11'd5) begin
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if (sd_dat_in[0]) begin
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if (blocks_remaining == 8'd0) begin
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next_state = STATE_IDLE;
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end else begin
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next_state = STATE_TX_WAIT;
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end
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end
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end
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end
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end
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endcase
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end
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// CRC16 units
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logic crc_reset;
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logic crc_enable;
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logic crc_shift;
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logic [3:0] crc_data;
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logic [15:0] crc_result [0:3];
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sd_crc_16 sd_crc_16_inst_0 (
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.clk(clk),
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.reset(crc_reset),
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.enable(crc_enable),
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.shift(crc_shift),
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.data(crc_data[0]),
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.result(crc_result[0])
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);
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sd_crc_16 sd_crc_16_inst_1 (
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.clk(clk),
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.reset(crc_reset),
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.enable(crc_enable),
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.shift(crc_shift),
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.data(crc_data[1]),
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.result(crc_result[1])
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);
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sd_crc_16 sd_crc_16_inst_2 (
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.clk(clk),
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.reset(crc_reset),
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.enable(crc_enable),
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.shift(crc_shift),
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.data(crc_data[2]),
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.result(crc_result[2])
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);
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sd_crc_16 sd_crc_16_inst_3 (
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.clk(clk),
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.reset(crc_reset),
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.enable(crc_enable),
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.shift(crc_shift),
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.data(crc_data[3]),
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.result(crc_result[3])
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);
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// Data shifting
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logic [7:0] data_shift;
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logic tx_rdata_valid;
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assign crc_data = (state == STATE_RX) ? rx_wdata[3:0] : sd_dat_data;
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always_comb begin
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tx_read = (state == STATE_TX) && sd_clk_falling && (counter < 11'd1024) && (!counter[0]);
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end
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always_ff @(posedge clk) begin
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rx_write <= 1'b0;
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tx_rdata_valid <= tx_read;
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crc_reset <= 1'b0;
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crc_enable <= 1'b0;
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crc_shift <= 1'b0;
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if (reset || sd_scb.dat_stop) begin
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sd_scb.clock_stop <= 1'b0;
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sd_dat_oe_data <= 1'b0;
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sd_dat_data <= 4'hF;
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end else begin
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case (state)
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STATE_IDLE: begin
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if (sd_scb.dat_start_read || sd_scb.dat_start_write) begin
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sd_scb.dat_error <= 1'b0;
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blocks_remaining <= sd_scb.dat_blocks;
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end
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end
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STATE_RX_WAIT: begin
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if (sd_scb.rx_count <= 11'd512) begin
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sd_scb.clock_stop <= 1'b0;
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end
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if (sd_clk_rising) begin
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if (!sd_dat_in[0]) begin
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counter <= 11'd1;
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crc_reset <= 1'b1;
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end
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end
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end
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STATE_RX: begin
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if (sd_clk_rising) begin
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counter <= counter + 1'd1;
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rx_wdata <= {rx_wdata[3:0], sd_dat_in};
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if (counter <= 11'd1024) begin
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crc_enable <= 1'b1;
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if (!counter[0]) begin
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if (rx_full) begin
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sd_scb.dat_error <= 1'b1;
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end else begin
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rx_write <= 1'b1;
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end
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end
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end else begin
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crc_shift <= 1'b1;
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if ({crc_result[3][15], crc_result[2][15], crc_result[1][15], crc_result[0][15]} != sd_dat_in) begin
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sd_scb.dat_error <= 1'b1;
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end
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end
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if (counter == 11'd1041) begin
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if ((blocks_remaining > 8'd0) && (sd_scb.rx_count > 11'd512)) begin
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sd_scb.clock_stop <= 1'b1;
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end
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blocks_remaining <= blocks_remaining - 1'd1;
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end
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end
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end
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STATE_TX_WAIT: begin
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if (sd_clk_falling) begin
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if (sd_scb.tx_count >= 11'd512) begin
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counter <= 11'd0;
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end
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end
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end
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STATE_TX: begin
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if (sd_clk_falling) begin
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counter <= counter + 1'd1;
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if (counter == 11'd0) begin
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crc_reset <= 1'b1;
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sd_dat_oe_data <= 1'b1;
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sd_dat_data <= 4'h0;
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end else if (counter <= 11'd1024) begin
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crc_enable <= 1'b1;
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{sd_dat_data, data_shift} <= {data_shift, 4'h0};
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end else begin
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crc_shift <= 1'b1;
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sd_dat_data <= {crc_result[3][15], crc_result[2][15], crc_result[1][15], crc_result[0][15]};
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end
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if (counter == 11'd1042) begin
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sd_dat_oe_data <= 1'b0;
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counter <= 11'd0;
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end
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end
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end
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STATE_TX_STATUS_WAIT: begin
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if (sd_clk_rising) begin
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counter <= counter + 1'd1;
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if (counter == 11'd8) begin
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sd_scb.dat_error <= 1'b1;
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end else if (!sd_dat_in[0]) begin
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counter <= 11'd1;
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end
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end
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end
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STATE_TX_STATUS: begin
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if (sd_clk_rising) begin
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if (counter < 11'd5) begin
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counter <= counter + 1'd1;
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end
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if ((counter == 11'd1) && (sd_dat_in[0] != 1'b0)) begin
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sd_scb.dat_error <= 1'b1;
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end
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if ((counter == 11'd2) && (sd_dat_in[0] != 1'b1)) begin
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sd_scb.dat_error <= 1'b1;
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end
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if ((counter == 11'd3) && (sd_dat_in[0] != 1'b0)) begin
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sd_scb.dat_error <= 1'b1;
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end
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if ((counter == 11'd4) && (sd_dat_in[0] != 1'b1)) begin
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sd_scb.dat_error <= 1'b1;
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end
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if ((counter == 11'd5) && (sd_dat_in[0] == 1'b1)) begin
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blocks_remaining <= blocks_remaining - 1'd1;
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end
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end
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end
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endcase
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end
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if (tx_rdata_valid) begin
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data_shift <= tx_rdata;
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end
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end
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endmodule
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