mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-05 03:14:15 +01:00
94 lines
2.0 KiB
Systemverilog
94 lines
2.0 KiB
Systemverilog
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interface sd_scb ();
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logic [1:0] clock_mode;
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logic clock_stop;
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logic card_busy;
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logic [10:0] rx_count;
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logic [10:0] tx_count;
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logic [5:0] cmd_index;
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logic [31:0] cmd_arg;
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logic [127:0] cmd_rsp;
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logic cmd_start;
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logic cmd_skip_response;
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logic cmd_reserved_response;
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logic cmd_long_response;
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logic cmd_ignore_crc;
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logic cmd_busy;
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logic cmd_error;
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logic dat_fifo_flush;
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logic dat_start_write;
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logic dat_start_read;
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logic dat_stop;
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logic [7:0] dat_blocks;
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logic dat_busy;
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logic dat_error;
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modport controller (
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output clock_mode,
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input card_busy,
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input rx_count,
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input tx_count,
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output cmd_index,
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output cmd_arg,
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input cmd_rsp,
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output cmd_start,
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output cmd_skip_response,
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output cmd_reserved_response,
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output cmd_long_response,
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output cmd_ignore_crc,
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input cmd_busy,
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input cmd_error,
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output dat_fifo_flush,
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output dat_start_write,
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output dat_start_read,
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output dat_stop,
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output dat_blocks,
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input dat_busy,
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input dat_error
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);
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modport clk (
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input clock_mode,
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input clock_stop
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);
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modport cmd (
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input cmd_index,
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input cmd_arg,
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output cmd_rsp,
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input cmd_start,
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input cmd_skip_response,
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input cmd_reserved_response,
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input cmd_long_response,
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input cmd_ignore_crc,
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output cmd_busy,
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output cmd_error
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);
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modport dat (
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output clock_stop,
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output card_busy,
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output rx_count,
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output tx_count,
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input dat_fifo_flush,
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input dat_start_write,
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input dat_start_read,
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input dat_stop,
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input dat_blocks,
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output dat_busy,
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output dat_error
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);
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endinterface
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