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https://github.com/Polprzewodnikowy/SummerCart64.git
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56 lines
930 B
Systemverilog
56 lines
930 B
Systemverilog
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module sd_top (
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input clk,
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input reset,
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sd_scb sd_scb,
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fifo_bus.fifo fifo_bus,
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output sd_clk,
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inout sd_cmd,
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inout [3:0] sd_dat
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);
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logic sd_clk_rising;
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logic sd_clk_falling;
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sd_clk sd_clk_inst (
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.clk(clk),
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.reset(reset),
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.sd_scb(sd_scb),
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.sd_clk_rising(sd_clk_rising),
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.sd_clk_falling(sd_clk_falling),
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.sd_clk(sd_clk)
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);
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sd_cmd sd_cmd_inst (
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.clk(clk),
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.reset(reset),
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.sd_scb(sd_scb),
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.sd_clk_rising(sd_clk_rising),
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.sd_clk_falling(sd_clk_falling),
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.sd_cmd(sd_cmd)
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);
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sd_dat sd_dat_inst (
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.clk(clk),
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.reset(reset),
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.sd_scb(sd_scb),
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.fifo_bus(fifo_bus),
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.sd_clk_rising(sd_clk_rising),
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.sd_clk_falling(sd_clk_falling),
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.sd_dat(sd_dat)
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);
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endmodule
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