mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
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143 lines
3.9 KiB
Coq
143 lines
3.9 KiB
Coq
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`default_nettype none
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module serv_csr
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#(parameter RESET_STRATEGY = "MINI")
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(
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input wire i_clk,
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input wire i_rst,
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//State
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input wire i_trig_irq,
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input wire i_en,
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input wire i_cnt0to3,
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input wire i_cnt3,
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input wire i_cnt7,
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input wire i_cnt_done,
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input wire i_mem_op,
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input wire i_mtip,
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input wire i_trap,
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output reg o_new_irq,
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//Control
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input wire i_e_op,
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input wire i_ebreak,
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input wire i_mem_cmd,
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input wire i_mstatus_en,
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input wire i_mie_en,
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input wire i_mcause_en,
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input wire [1:0] i_csr_source,
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input wire i_mret,
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input wire i_csr_d_sel,
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//Data
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input wire i_rf_csr_out,
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output wire o_csr_in,
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input wire i_csr_imm,
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input wire i_rs1,
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output wire o_q);
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localparam [1:0]
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CSR_SOURCE_CSR = 2'b00,
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CSR_SOURCE_EXT = 2'b01,
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CSR_SOURCE_SET = 2'b10,
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CSR_SOURCE_CLR = 2'b11;
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reg mstatus_mie;
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reg mstatus_mpie;
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reg mie_mtie;
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reg mcause31;
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reg [3:0] mcause3_0;
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wire mcause;
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wire csr_in;
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wire csr_out;
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reg timer_irq_r;
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wire d = i_csr_d_sel ? i_csr_imm : i_rs1;
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assign csr_in = (i_csr_source == CSR_SOURCE_EXT) ? d :
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(i_csr_source == CSR_SOURCE_SET) ? csr_out | d :
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(i_csr_source == CSR_SOURCE_CLR) ? csr_out & ~d :
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(i_csr_source == CSR_SOURCE_CSR) ? csr_out :
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1'bx;
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assign csr_out = (i_mstatus_en & mstatus_mie & i_cnt3) |
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i_rf_csr_out |
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(i_mcause_en & i_en & mcause);
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assign o_q = csr_out;
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wire timer_irq = i_mtip & mstatus_mie & mie_mtie;
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assign mcause = i_cnt0to3 ? mcause3_0[0] : //[3:0]
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i_cnt_done ? mcause31 //[31]
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: 1'b0;
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assign o_csr_in = csr_in;
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always @(posedge i_clk) begin
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if (i_trig_irq) begin
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timer_irq_r <= timer_irq;
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o_new_irq <= timer_irq & !timer_irq_r;
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end
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if (i_mie_en & i_cnt7)
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mie_mtie <= csr_in;
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/*
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The mie bit in mstatus gets updated under three conditions
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When a trap is taken, the bit is cleared
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During an mret instruction, the bit is restored from mpie
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During a mstatus CSR access instruction it's assigned when
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bit 3 gets updated
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These conditions are all mutually exclusibe
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*/
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if ((i_trap & i_cnt_done) | i_mstatus_en & i_cnt3 | i_mret)
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mstatus_mie <= !i_trap & (i_mret ? mstatus_mpie : csr_in);
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/*
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Note: To save resources mstatus_mpie (mstatus bit 7) is not
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readable or writable from sw
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*/
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if (i_trap & i_cnt_done)
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mstatus_mpie <= mstatus_mie;
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/*
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The four lowest bits in mcause hold the exception code
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These bits get updated under three conditions
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During an mcause CSR access function, they are assigned when
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bits 0 to 3 gets updated
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During an external interrupt the exception code is set to
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7, since SERV only support timer interrupts
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During an exception, the exception code is assigned to indicate
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if it was caused by an ebreak instruction (3),
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ecall instruction (11), misaligned load (4), misaligned store (6)
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or misaligned jump (0)
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The expressions below are derived from the following truth table
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irq => 0111 (timer=7)
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e_op => x011 (ebreak=3, ecall=11)
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mem => 01x0 (store=6, load=4)
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ctrl => 0000 (jump=0)
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*/
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if (i_mcause_en & i_en & i_cnt0to3 | (i_trap & i_cnt_done)) begin
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mcause3_0[3] <= (i_e_op & !i_ebreak) | (!i_trap & csr_in);
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mcause3_0[2] <= o_new_irq | i_mem_op | (!i_trap & mcause3_0[3]);
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mcause3_0[1] <= o_new_irq | i_e_op | (i_mem_op & i_mem_cmd) | (!i_trap & mcause3_0[2]);
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mcause3_0[0] <= o_new_irq | i_e_op | (!i_trap & mcause3_0[1]);
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end
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if (i_mcause_en & i_cnt_done | i_trap)
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mcause31 <= i_trap ? o_new_irq : csr_in;
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if (i_rst)
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if (RESET_STRATEGY != "NONE") begin
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o_new_irq <= 1'b0;
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mie_mtie <= 1'b0;
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end
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end
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endmodule
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