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https://github.com/Polprzewodnikowy/SummerCart64.git
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175 lines
4.0 KiB
Coq
175 lines
4.0 KiB
Coq
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`default_nettype none
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module serv_rf_ram_if
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#(//Data width. Adjust to preferred width of SRAM data interface
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parameter width=8,
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//Select reset strategy.
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// "MINI" for resetting minimally required FFs
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// "NONE" for relying on FFs having a defined value on startup
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parameter reset_strategy="MINI",
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//Number of CSR registers. These are allocated after the normal
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// GPR registers in the RAM.
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parameter csr_regs=4,
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//Internal parameters calculated from above values. Do not change
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parameter raw=$clog2(32+csr_regs), //Register address width
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parameter l2w=$clog2(width), //log2 of width
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parameter aw=5+raw-l2w) //Address width
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(
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//SERV side
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input wire i_clk,
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input wire i_rst,
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input wire i_wreq,
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input wire i_rreq,
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output wire o_ready,
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input wire [raw-1:0] i_wreg0,
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input wire [raw-1:0] i_wreg1,
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input wire i_wen0,
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input wire i_wen1,
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input wire i_wdata0,
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input wire i_wdata1,
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input wire [raw-1:0] i_rreg0,
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input wire [raw-1:0] i_rreg1,
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output wire o_rdata0,
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output wire o_rdata1,
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//RAM side
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output wire [aw-1:0] o_waddr,
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output wire [width-1:0] o_wdata,
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output wire o_wen,
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output wire [aw-1:0] o_raddr,
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output wire o_ren,
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input wire [width-1:0] i_rdata);
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reg rgnt;
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assign o_ready = rgnt | i_wreq;
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reg [4:0] rcnt;
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reg rtrig1;
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/*
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********** Write side ***********
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*/
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wire [4:0] wcnt;
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reg [width-1:0] wdata0_r;
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reg [width-0:0] wdata1_r;
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reg wen0_r;
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reg wen1_r;
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wire wtrig0;
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wire wtrig1;
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assign wtrig0 = rtrig1;
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generate if (width == 2) begin : gen_w_eq_2
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assign wtrig1 = wcnt[0];
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end else begin : gen_w_neq_2
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reg wtrig0_r;
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always @(posedge i_clk) wtrig0_r <= wtrig0;
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assign wtrig1 = wtrig0_r;
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end
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endgenerate
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assign o_wdata = wtrig1 ?
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wdata1_r[width-1:0] :
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wdata0_r;
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wire [raw-1:0] wreg = wtrig1 ? i_wreg1 : i_wreg0;
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generate if (width == 32) begin : gen_w_eq_32
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assign o_waddr = wreg;
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end else begin : gen_w_neq_32
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assign o_waddr = {wreg, wcnt[4:l2w]};
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end
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endgenerate
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assign o_wen = (wtrig0 & wen0_r) | (wtrig1 & wen1_r);
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assign wcnt = rcnt-4;
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always @(posedge i_clk) begin
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if (wcnt[0]) begin
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wen0_r <= i_wen0;
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wen1_r <= i_wen1;
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end
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wdata0_r <= {i_wdata0,wdata0_r[width-1:1]};
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wdata1_r <= {i_wdata1,wdata1_r[width-0:1]};
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end
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/*
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********** Read side ***********
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*/
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wire rtrig0;
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wire [raw-1:0] rreg = rtrig0 ? i_rreg1 : i_rreg0;
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generate if (width == 32) begin : gen_rreg_eq_32
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assign o_raddr = rreg;
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end else begin : gen_rreg_neq_32
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assign o_raddr = {rreg, rcnt[4:l2w]};
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end
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endgenerate
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reg [width-1:0] rdata0;
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reg [width-2:0] rdata1;
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reg rgate;
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assign o_rdata0 = rdata0[0];
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assign o_rdata1 = rtrig1 ? i_rdata[0] : rdata1[0];
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assign rtrig0 = (rcnt[l2w-1:0] == 1);
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generate if (width == 2) begin : gen_ren_w_eq_2
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assign o_ren = rgate;
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end else begin : gen_ren_w_neq_2
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assign o_ren = rgate & (rcnt[l2w-1:1] == 0);
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end
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endgenerate
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reg rreq_r;
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generate if (width>2) begin : gen_rdata1_w_neq_2
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always @(posedge i_clk) begin
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rdata1 <= {1'b0,rdata1[width-2:1]}; //Optimize?
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if (rtrig1)
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rdata1[width-2:0] <= i_rdata[width-1:1];
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end
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end else begin : gen_rdata1_w_eq_2
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always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1];
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end
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endgenerate
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always @(posedge i_clk) begin
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if (&rcnt | i_rreq)
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rgate <= i_rreq;
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rtrig1 <= rtrig0;
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rcnt <= rcnt+5'd1;
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if (i_rreq | i_wreq)
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rcnt <= {3'd0,i_wreq,1'b0};
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rreq_r <= i_rreq;
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rgnt <= rreq_r;
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rdata0 <= {1'b0,rdata0[width-1:1]};
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if (rtrig0)
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rdata0 <= i_rdata;
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if (i_rst) begin
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if (reset_strategy != "NONE") begin
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rgate <= 1'b0;
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rgnt <= 1'b0;
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rreq_r <= 1'b0;
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rcnt <= 5'd0;
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end
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end
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end
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endmodule
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