mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-23 14:29:14 +01:00
58 lines
1.2 KiB
Systemverilog
58 lines
1.2 KiB
Systemverilog
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module n64_soc (
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if_system sys,
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if_config cfg,
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input n64_pi_alel,
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input n64_pi_aleh,
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input n64_pi_read,
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input n64_pi_write,
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inout [15:0] n64_pi_ad,
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input n64_si_clk,
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inout n64_si_dq,
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output sdram_clk,
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output sdram_cs,
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output sdram_ras,
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output sdram_cas,
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output sdram_we,
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output [1:0] sdram_ba,
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output [12:0] sdram_a,
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inout [15:0] sdram_dq
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);
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if_n64_bus bus ();
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n64_pi n64_pi_inst (
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.sys(sys),
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.cfg(cfg),
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.bus(bus),
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.n64_pi_alel(n64_pi_alel),
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.n64_pi_aleh(n64_pi_aleh),
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.n64_pi_read(n64_pi_read),
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.n64_pi_write(n64_pi_write),
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.n64_pi_ad(n64_pi_ad)
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);
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memory_sdram memory_sdram_inst (
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.sys(sys),
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.bus(bus.at[sc64::ID_N64_SDRAM].device),
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.sdram_clk(sdram_clk),
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.sdram_cs(sdram_cs),
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.sdram_ras(sdram_ras),
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.sdram_cas(sdram_cas),
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.sdram_we(sdram_we),
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.sdram_ba(sdram_ba),
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.sdram_a(sdram_a),
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.sdram_dq(sdram_dq)
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);
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memory_flash memory_flash_inst (
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.sys(sys),
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.bus(bus.at[sc64::ID_N64_BOOTLOADER].device)
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);
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endmodule
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