mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
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72 lines
1.3 KiB
Plaintext
72 lines
1.3 KiB
Plaintext
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[*]
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[*] GTKWave Analyzer v3.3.65 (w)1999-2015 BSI
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[*] Fri Aug 26 15:42:37 2016
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[*]
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[dumpfile] "/home/clifford/Work/picorv32/scripts/smtbmc/output.vcd"
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[dumpfile_mtime] "Fri Aug 26 15:33:18 2016"
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[dumpfile_size] 80106
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[savefile] "/home/clifford/Work/picorv32/scripts/smtbmc/tracecmp.gtkw"
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[timestart] 0
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[size] 1216 863
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[pos] -1 -1
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*-2.860312 10 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] testbench.
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[sst_width] 241
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[signals_width] 337
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[sst_expanded] 1
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[sst_vpaned_height] 252
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@28
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smt_clock
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testbench.resetn
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testbench.trap_0
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testbench.trap_1
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@200
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-
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-Trace CMP
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@28
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testbench.trace_valid_0
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testbench.trace_valid_1
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@22
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testbench.trace_data_0[35:0]
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testbench.trace_data_1[35:0]
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@420
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testbench.trace_balance[7:0]
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@200
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-
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-CPU #0
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@28
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testbench.mem_valid_0
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testbench.mem_ready_0
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testbench.mem_instr_0
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@22
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testbench.mem_addr_0[31:0]
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testbench.mem_rdata_0[31:0]
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testbench.mem_wdata_0[31:0]
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@28
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testbench.mem_wstrb_0[3:0]
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@22
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testbench.cpu_0.cpu_state[7:0]
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@28
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testbench.cpu_0.mem_state[1:0]
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@200
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-
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-CPU #1
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@28
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testbench.mem_valid_1
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testbench.mem_ready_1
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testbench.mem_instr_1
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@22
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testbench.mem_addr_1[31:0]
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testbench.mem_rdata_1[31:0]
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testbench.mem_wdata_1[31:0]
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@28
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testbench.mem_wstrb_1[3:0]
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@22
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testbench.cpu_1.cpu_state[7:0]
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@28
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testbench.cpu_1.mem_state[1:0]
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@200
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-
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[pattern_trace] 1
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[pattern_trace] 0
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