mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-27 13:31:53 +01:00
84 lines
2.7 KiB
ArmAsm
84 lines
2.7 KiB
ArmAsm
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# See LICENSE for license details.
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#*****************************************************************************
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# sub.S
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#-----------------------------------------------------------------------------
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#
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# Test sub instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Arithmetic tests
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#-------------------------------------------------------------
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TEST_RR_OP( 2, sub, 0x00000000, 0x00000000, 0x00000000 );
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TEST_RR_OP( 3, sub, 0x00000000, 0x00000001, 0x00000001 );
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TEST_RR_OP( 4, sub, 0xfffffffc, 0x00000003, 0x00000007 );
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TEST_RR_OP( 5, sub, 0x00008000, 0x00000000, 0xffff8000 );
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TEST_RR_OP( 6, sub, 0x80000000, 0x80000000, 0x00000000 );
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TEST_RR_OP( 7, sub, 0x80008000, 0x80000000, 0xffff8000 );
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TEST_RR_OP( 8, sub, 0xffff8001, 0x00000000, 0x00007fff );
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TEST_RR_OP( 9, sub, 0x7fffffff, 0x7fffffff, 0x00000000 );
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TEST_RR_OP( 10, sub, 0x7fff8000, 0x7fffffff, 0x00007fff );
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TEST_RR_OP( 11, sub, 0x7fff8001, 0x80000000, 0x00007fff );
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TEST_RR_OP( 12, sub, 0x80007fff, 0x7fffffff, 0xffff8000 );
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TEST_RR_OP( 13, sub, 0x00000001, 0x00000000, 0xffffffff );
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TEST_RR_OP( 14, sub, 0xfffffffe, 0xffffffff, 0x00000001 );
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TEST_RR_OP( 15, sub, 0x00000000, 0xffffffff, 0xffffffff );
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#-------------------------------------------------------------
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# Source/Destination tests
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#-------------------------------------------------------------
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TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 );
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TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 );
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TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 );
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#-------------------------------------------------------------
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# Bypassing tests
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#-------------------------------------------------------------
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TEST_RR_DEST_BYPASS( 19, 0, sub, 2, 13, 11 );
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TEST_RR_DEST_BYPASS( 20, 1, sub, 3, 14, 11 );
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TEST_RR_DEST_BYPASS( 21, 2, sub, 4, 15, 11 );
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TEST_RR_SRC12_BYPASS( 22, 0, 0, sub, 2, 13, 11 );
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TEST_RR_SRC12_BYPASS( 23, 0, 1, sub, 3, 14, 11 );
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TEST_RR_SRC12_BYPASS( 24, 0, 2, sub, 4, 15, 11 );
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TEST_RR_SRC12_BYPASS( 25, 1, 0, sub, 2, 13, 11 );
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TEST_RR_SRC12_BYPASS( 26, 1, 1, sub, 3, 14, 11 );
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TEST_RR_SRC12_BYPASS( 27, 2, 0, sub, 4, 15, 11 );
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TEST_RR_SRC21_BYPASS( 28, 0, 0, sub, 2, 13, 11 );
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TEST_RR_SRC21_BYPASS( 29, 0, 1, sub, 3, 14, 11 );
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TEST_RR_SRC21_BYPASS( 30, 0, 2, sub, 4, 15, 11 );
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TEST_RR_SRC21_BYPASS( 31, 1, 0, sub, 2, 13, 11 );
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TEST_RR_SRC21_BYPASS( 32, 1, 1, sub, 3, 14, 11 );
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TEST_RR_SRC21_BYPASS( 33, 2, 0, sub, 4, 15, 11 );
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TEST_RR_ZEROSRC1( 34, sub, 15, -15 );
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TEST_RR_ZEROSRC2( 35, sub, 32, 32 );
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TEST_RR_ZEROSRC12( 36, sub, 0 );
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TEST_RR_ZERODEST( 37, sub, 16, 30 );
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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