mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-28 16:34:14 +01:00
73 lines
1.5 KiB
Systemverilog
73 lines
1.5 KiB
Systemverilog
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interface if_system (
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input in_clk,
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input n64_reset,
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input n64_nmi
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);
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logic clk;
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logic sdram_clk;
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logic reset;
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logic n64_soft_reset;
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logic n64_hard_reset;
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modport internal (
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input in_clk,
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input n64_reset,
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input n64_nmi,
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output clk,
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output sdram_clk,
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output reset,
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output n64_soft_reset,
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output n64_hard_reset
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);
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modport sys (
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input clk,
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input reset,
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input n64_soft_reset,
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input n64_hard_reset
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);
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modport sdram (
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input sdram_clk
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);
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endinterface
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module system (if_system.internal sys);
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logic locked;
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logic external_reset;
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logic [1:0] n64_reset_ff;
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logic [1:0] n64_nmi_ff;
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intel_pll intel_pll_inst (
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.inclk0(sys.in_clk),
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.c0(sys.clk),
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.c1(sys.sdram_clk),
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.locked(locked)
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);
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generate
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if (sc64::DEBUG_ENABLED) begin
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intel_snp intel_snp_inst (
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.source(external_reset),
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.source_clk(sys.clk)
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);
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end
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endgenerate
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always_ff @(posedge sys.clk) begin
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n64_reset_ff <= {n64_reset_ff[0], sys.n64_reset};
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n64_nmi_ff <= {n64_nmi_ff[0], sys.n64_nmi};
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end
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always_comb begin
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sys.reset = ~locked | external_reset;
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sys.n64_hard_reset = ~n64_reset_ff[1];
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sys.n64_soft_reset = ~n64_nmi_ff[1];
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end
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endmodule
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