mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-27 16:14:13 +01:00
124 lines
6.8 KiB
Coq
124 lines
6.8 KiB
Coq
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// megafunction wizard: %GPIO Lite Intel FPGA IP v20.1%
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// GENERATION: XML
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// intel_gpio_ddro.v
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// Generated using ACDS version 20.1 720
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`timescale 1 ps / 1 ps
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module intel_gpio_ddro (
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input wire outclock, // outclock.export
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input wire [1:0] din, // din.export
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output wire [0:0] pad_out // pad_out.export
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);
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altera_gpio_lite #(
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.PIN_TYPE ("output"),
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.SIZE (1),
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.REGISTER_MODE ("ddr"),
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.BUFFER_TYPE ("single-ended"),
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.ASYNC_MODE ("none"),
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.SYNC_MODE ("none"),
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.BUS_HOLD ("false"),
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.OPEN_DRAIN_OUTPUT ("false"),
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.ENABLE_OE_PORT ("false"),
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.ENABLE_NSLEEP_PORT ("false"),
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.ENABLE_CLOCK_ENA_PORT ("false"),
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.SET_REGISTER_OUTPUTS_HIGH ("false"),
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.INVERT_OUTPUT ("false"),
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.INVERT_INPUT_CLOCK ("false"),
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.USE_ONE_REG_TO_DRIVE_OE ("false"),
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.USE_DDIO_REG_TO_DRIVE_OE ("false"),
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.USE_ADVANCED_DDR_FEATURES ("false"),
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.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"),
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.ENABLE_OE_HALF_CYCLE_DELAY ("true"),
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.INVERT_CLKDIV_INPUT_CLOCK ("false"),
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.ENABLE_PHASE_INVERT_CTRL_PORT ("false"),
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.ENABLE_HR_CLOCK ("false"),
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.INVERT_OUTPUT_CLOCK ("false"),
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.INVERT_OE_INCLOCK ("false"),
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.ENABLE_PHASE_DETECTOR_FOR_CK ("false")
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) intel_gpio_ddro_inst (
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.outclock (outclock), // outclock.export
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.din (din), // din.export
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.pad_out (pad_out), // pad_out.export
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.outclocken (1'b1), // (terminated)
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.inclock (1'b0), // (terminated)
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.inclocken (1'b0), // (terminated)
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.fr_clock (), // (terminated)
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.hr_clock (), // (terminated)
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.invert_hr_clock (1'b0), // (terminated)
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.phy_mem_clock (1'b0), // (terminated)
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.mimic_clock (), // (terminated)
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.dout (), // (terminated)
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.pad_io (), // (terminated)
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.pad_io_b (), // (terminated)
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.pad_in (1'b0), // (terminated)
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.pad_in_b (1'b0), // (terminated)
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.pad_out_b (), // (terminated)
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.aset (1'b0), // (terminated)
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.aclr (1'b0), // (terminated)
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.sclr (1'b0), // (terminated)
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.nsleep (1'b0), // (terminated)
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.oe (1'b0) // (terminated)
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);
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endmodule
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// Retrieval info: <?xml version="1.0"?>
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//<!--
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// Generated by Altera MegaWizard Launcher Utility version 1.0
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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// ************************************************************
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// Copyright (C) 1991-2021 Altera Corporation
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// Any megafunction design, and related net list (encrypted or decrypted),
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// support information, device programming or simulation file, and any other
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// associated documentation or information provided by Altera or a partner
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// under Altera's Megafunction Partnership Program may be used only to
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// program PLD devices (but not masked PLD devices) from Altera. Any other
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// use of such megafunction design, net list, support information, device
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// programming or simulation file, or any other related documentation or
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// information is prohibited for any other purpose, including, but not
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// limited to modification, reverse engineering, de-compiling, or use with
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// any other silicon devices, unless such use is explicitly licensed under
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// a separate agreement with Altera or a megafunction partner. Title to
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// the intellectual property, including patents, copyrights, trademarks,
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// trade secrets, or maskworks, embodied in any such megafunction design,
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// net list, support information, device programming or simulation file, or
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// any other related documentation or information provided by Altera or a
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// megafunction partner, remains with Altera, the megafunction partner, or
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// their respective licensors. No other licenses, including any licenses
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// needed under any third party's intellectual property, are provided herein.
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//-->
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// Retrieval info: <instance entity-name="altera_gpio_lite" version="20.1" >
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// Retrieval info: <generic name="DEVICE_FAMILY" value="MAX 10" />
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// Retrieval info: <generic name="PIN_TYPE" value="output" />
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// Retrieval info: <generic name="SIZE" value="1" />
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// Retrieval info: <generic name="gui_true_diff_buf" value="false" />
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// Retrieval info: <generic name="gui_pseudo_diff_buf" value="false" />
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// Retrieval info: <generic name="gui_bus_hold" value="false" />
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// Retrieval info: <generic name="gui_open_drain" value="false" />
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// Retrieval info: <generic name="gui_enable_oe_port" value="false" />
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// Retrieval info: <generic name="gui_enable_nsleep_port" value="false" />
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// Retrieval info: <generic name="gui_io_reg_mode" value="ddr" />
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// Retrieval info: <generic name="gui_enable_aclr_port" value="false" />
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// Retrieval info: <generic name="gui_enable_aset_port" value="false" />
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// Retrieval info: <generic name="gui_enable_sclr_port" value="false" />
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// Retrieval info: <generic name="gui_set_registers_to_power_up_high" value="false" />
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// Retrieval info: <generic name="gui_clock_enable" value="false" />
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// Retrieval info: <generic name="gui_invert_output" value="false" />
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// Retrieval info: <generic name="gui_invert_input_clock" value="false" />
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// Retrieval info: <generic name="gui_use_register_to_drive_obuf_oe" value="false" />
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// Retrieval info: <generic name="gui_use_ddio_reg_to_drive_oe" value="false" />
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// Retrieval info: <generic name="gui_use_advanced_ddr_features" value="false" />
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// Retrieval info: <generic name="gui_enable_phase_detector_for_ck" value="false" />
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// Retrieval info: <generic name="gui_enable_oe_half_cycle_delay" value="true" />
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// Retrieval info: <generic name="gui_enable_hr_clock" value="false" />
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// Retrieval info: <generic name="gui_enable_invert_hr_clock_port" value="false" />
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// Retrieval info: <generic name="gui_invert_clkdiv_input_clock" value="false" />
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// Retrieval info: <generic name="gui_invert_output_clock" value="false" />
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// Retrieval info: <generic name="gui_invert_oe_inclock" value="false" />
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// Retrieval info: <generic name="gui_use_hardened_ddio_input_registers" value="false" />
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// Retrieval info: </instance>
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// IPFS_FILES : intel_gpio_ddro.vo
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// RELATED_FILES: intel_gpio_ddro.v, altera_gpio_lite.sv
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