2 kB of EEPROM Memory. Available on the bus when **EEPROM_PI** bit in **CART->CR** register is set. Used to upload/download EEPROM contents to/from PC.
1 kB of RX FIFO. Available on the bus when **DEBUG** bit in **CART->CR** register is set. Used to receive arbitrary data from PC. Only 4 byte reads are supported, for single byte reads use **CART->DEBUG_RX** register.
#### TX FIFO DMA Memory (unimplemented)
Base address: **`0x1D100 0800`**\
Length: **`1kB`**\
Access: Write only, 4 byte (32 bit) aligned
1 kB of TX FIFO. Available on the bus when **DEBUG** bit in **CART->CR** register is set. Used to send arbitrary data to PC. Only 4 byte writes are supported, for single byte writes use **CART->DEBUG_TX** register.
- Bit 4 **EEPROM_16K**: Sets ID returned by EEPROM to identify itself as 4k or 16k variant.
- 0: EEPROM 4k variant
- 1: EEPROM 16k variant
- Bit 3 **EEPROM_SI**: Enable EEPROM access through SI bus.
- 0: EEPROM SI access disabled
- 1: EEPROM SI access enabled
- Bit 2 **EEPROM_PI**: Enable EEPROM access through PI bus at address base **`0x1D00 0000`**. Cleared by hardware on N64 Reset/NMI event.
- 0: EEPROM PI access disabled
- 1: EEPROM PI access enabled
- Bit 1 **SDRAM**: Enable SDRAM access at address base **`0x1000 0000`**. This bit also remaps Flash base address. Cleared by hardware on N64 Reset/NMI event.
- 0: SDRAM disabled
- 1: SDRAM enabled
- Bit 0 **FLASH**: Enable Flash access at address base **`0x1000 0000`** (**SDRAM** = 0) or **`0x1800 0000`** (**SDRAM** = 1). Set by hardware on N64 Reset/NMI event.
- 0: Flash disabled
- 1: Flash enabled
#### CIC and TV type override register (**CIC_TV**)
Address offset: **`0x04`**\
Powerup value: **`0x0000 0000`**\
Access: Read or write, 4 byte (32 bit) aligned
This register is used for PC -> bootloader communication.
This register is used to send arbitrary commands to Flash chip, useful for erasing and programming memory from PC or N64. Extended register documentation is available at [this webpage](https://zipcpu.com/blog/2019/03/27/qflexpress.html).
Module contains two 1024 word (4 kB) FIFOs used as a gate between SPI clock domain and Cart clock domain. Debug communication uses its own set of FIFOs, 1 kB in size each.
Sets PC communication module bus controller configuration.
This command consumes space in TX FIFO. Check TX FIFO availability before issuing this command.
Command bytes:
Byte(s) | 0 | 1:4
-----------|------|--------------------
Value | 0x10 | Configuration word
Direction | W | W
Configuration word bits:
31:2 | 1 | 0
------|-----------|-------------
x | ADDR_INCR | N64_DISABLE
- Bits 31:2: Reserved. Writes are ignored but it's recommended to be set as 0 for future compatibility.
- Bit 1 **ADDR_INCR**: Sets address increment mode when reading or writing to bus. Useful for writing/reading many values to/from single address.
- 0: No address increment
- 1: Address increment
- Bit 0 **N64_DISABLE**: Disables N64 PI interface and enables communication module access to the bus.
- 0: N64 PI interface enabled, PC bus access disabled
- 1: N64 PI interface disabled, PC bus access enabled
Example - set address increment and disable N64:
Byte | 0 | 1 | 2 | 3 | 4
------|------|------|------|------|------
TX | 0x10 | 0x00 | 0x00 | 0x00 | 0x03
RX | x | x | x | x | x
*x = don't care*
#### Address (**0x20**)
Sets starting bus address.
This command consumes space in TX FIFO. Check TX FIFO availability before issuing this command.
Command bytes:
Byte(s) | 0 | 1:4
-----------|------|--------------
Value | 0x20 | Address word
Direction | W | W
Address word bits:
31:0 |
---------|
ADDRESS |
- Bits 31:0 **ADDRESS**: Starting address in bus address space.
Example - set starting address **`0x1034 5678`**:
Byte | 0 | 1 | 2 | 3 | 4
------|------|------|------|------|------
TX | 0x20 | 0x10 | 0x34 | 0x56 | 0x78
RX | x | x | x | x | x
*x = don't care*
#### Initiate read to RX FIFO (**0x30**)
Initiates read of X 4 byte (32 bit) words to RX FIFO. Maximum possible read length is 64 MB. However, it's possible to send multiple commands in series to achieve longer read lengths. After issuing this command it's necesarry to read data with "Read from RX FIFO (0x50)" command. Command will read dummy data when **N64_DISABLE** bit is cleared in communication module configuration.
This command consumes space in TX FIFO. Check TX FIFO availability before issuing this command.
Command bytes:
Byte(s) | 0 | 1:4
-----------|------|------------------
Value | 0x30 | Read length word
Direction | W | W
Read length word bits:
31:24 | 23:0 |
-------|-------------|
x | READ_LENGTH |
- Bits 31:24: Reserved. Writes are ignored but it's recommended to be set as 0 for future compatibility.
- Bits 23:0 **READ_LENGTH**: Number of words to be read to RX FIFO minus one.
Example - fill RX FIFO with 5 words (20 bytes):
Byte | 0 | 1 | 2 | 3 | 4
------|------|------|------|------|------
TX | 0x30 | 0x00 | 0x00 | 0x00 | 0x04
RX | x | x | x | x | x
*x = don't care*
#### Write to TX FIFO (**0x40**)
Writes data to TX FIFO. Sent words then are processed immediately as bus writes at current internal bus address. Data can be written only as 4 byte (32 bit) words. When **N64_DISABLE** bit in communication module configuration is cleared then command will process data in TX FIFO but it won't write anything to bus.
This command consumes space in TX FIFO. Check TX FIFO availability before issuing this command.
Reads data from RX FIFO. Data can be read only as 4 byte (32 bit) words. Before reading it's necessary to check RX FIFO availability. Reading empty FIFO won't break anything but it's pointless.
